DisplayPort Pixel Packing for 10-Bit and 12-Bit Color

This article examines how the DisplayPort interface manages pixel packing for 10-bit and 12-bit Deep Color data formats. It covers the serialization of non-byte-aligned RGB and YCbCr components, the multi-pixel repeating patterns required to align video streams with standard byte structures, and the distribution of these packed bytes across physical DisplayPort Main Link lanes.

The Alignment Challenge in Deep Color

DisplayPort transports digital video across its Main Link using byte-sized symbol units (8 bits in legacy 8b/10b encoding, or 16-bit/32-bit units mapped to 128b/132b encoding blocks in modern revisions). Standard 8-bit color per component (bpc) produces a 24-bit pixel (8 bits each for Red, Green, and Blue), which aligns naturally across three 8-bit bytes.

When transitioning to Deep Color:

  • 10-bit color (30 bpp): Three 10-bit color components result in 30 bits per pixel.
  • 12-bit color (36 bpp): Three 12-bit color components result in 36 bits per pixel.

Because neither 30 nor 36 is evenly divisible by 8, individual color components cannot map directly into standard byte boundaries without fragmentation. Rather than padding each component with unused bits—which would consume link bandwidth inefficiently—the DisplayPort standard packs sequential pixel components tightly across consecutive bytes.

10-Bit (30 bpp) Pixel Packing Mechanics

For 10-bit RGB or YCbCr 4:4:4 formats, DisplayPort achieves byte alignment using a repeating block of 4 pixels.

The calculation relies on finding the least common multiple between pixel size and byte size:

  • 4 pixels × 30 bits = 120 bits
  • 120 bits ÷ 8 bits = 15 bytes

In this scheme, four complete 10-bit pixels are packed into 15 sequential bytes. The components are serialized in order (R, G, B or Y, Cb, Cr), with the most significant bits (MSBs) transmitted first. Because individual 10-bit values cross byte boundaries:

  1. Byte 0 holds the 8 most significant bits of Pixel 0's Red component (\(R0[9:2]\)).
  2. Byte 1 holds the 2 remaining least significant bits of Pixel 0's Red component (\(R0[1:0]\)) combined with the 6 most significant bits of Pixel 0's Green component (\(G0[9:4]\)).
  3. Byte 2 takes the remaining 4 bits of Green (\(G0[3:0]\)) and the 4 most significant bits of Blue (\(B0[9:6]\)).
  4. This bit-slicing pattern continues across the payload until Byte 14 completes the Blue component of Pixel 3 (\(B3[1:0]\)), resetting the alignment for the next group of 4 pixels.

12-Bit (36 bpp) Pixel Packing Mechanics

For 12-bit color components, byte alignment occurs over a shorter cycle of 2 pixels:

  • 2 pixels × 36 bits = 72 bits
  • 72 bits ÷ 8 bits = 9 bytes

Two full 12-bit pixels are packed into 9 consecutive bytes. The alignment structure follows a consistent pattern:

  1. Byte 0 contains the upper 8 bits of Pixel 0's first component (\(R0[11:4]\)).
  2. Byte 1 contains the lower 4 bits of Pixel 0's first component (\(R0[3:0]\)) and the upper 4 bits of the second component (\(G0[11:8]\)).
  3. Byte 2 contains the lower 8 bits of the second component (\(G0[7:0]\)).
  4. Byte 3 contains the upper 8 bits of the third component (\(B0[11:4]\)).
  5. Byte 4 contains the lower 4 bits of the third component (\(B0[3:0]\)) and the upper 4 bits of Pixel 1's first component (\(R1[11:8]\)).

This alternating 8-bit/4-bit split repeats until Byte 8 completes the 72-bit cycle with the remaining 8 bits of Pixel 1's third component (\(B1[7:0]\)).

Once the pixel components are serialized into byte streams, DisplayPort distributes these bytes across its configured physical lanes (1, 2, or 4 lanes):

  • Round-Robin Allocation: Bytes are assigned cyclically across available lanes. In a 4-lane configuration, Byte 0 routes to Lane 0, Byte 1 to Lane 1, Byte 2 to Lane 2, Byte 3 to Lane 3, and Byte 4 loops back to Lane 0.
  • Transfer Units (TUs): The stream of packed pixel bytes is organized into Transfer Units (typically 32 to 64 link symbols in size). Framing symbols like FS (Fill Start) and FE (Fill End) are inserted to handle discrepancies between the incoming video pixel clock and the fixed link-symbol clock rate.
  • Line Boundaries: DisplayPort specifies that pixel packing sequences reset at the start of each active video line, ensuring that link receivers can re-synchronize component boundaries independently on every scan line.