DisplayPort PHY: Digital Logic to Electrical Signals

The DisplayPort Physical Layer (PHY) functions as the hardware bridge that transforms parallel digital data from a system's graphics pipeline into high-speed, serial electrical signals capable of traveling across a physical cable. This process involves a structured transmission pipeline encompassing data scrambling, line coding, serialization via high-speed clocking, and transmission through differential line drivers. By employing techniques like pre-emphasis and adaptive link training, the PHY ensures that high-bandwidth data arrives at the display receiver intact and free of signal degradation.

1. Data Scrambling

Before electrical transmission begins, the raw digital data stream—consisting of pixel data, audio, and control packets—is passed through a Linear Feedback Shift Register (LFSR) scrambler. This process randomizes repetitive data patterns (such as blocks of identical colors or blanking intervals). Scrambling prevents concentrated spectral energy, thereby reducing Electromagnetic Interference (EMI) and maintaining compliance with radio-frequency radiation standards without altering the underlying data payload.

2. Line Encoding

To ensure the receiver can properly decode the incoming data without a separate physical clock wire, the scrambled data undergoes line encoding. DisplayPort uses different encoding schemes depending on the standard's generation:

  • 8b/10b Encoding (RBR, HBR, HBR2, HBR3): Maps 8-bit data bytes onto 10-bit symbols. This overhead guarantees frequent bit transitions to allow clock data recovery (CDR) at the sink device and maintains DC balance by avoiding long runs of continuous 1s or 0s.
  • 128b/132b Encoding (UHBR 10, 13.5, 20): Used in DisplayPort 2.0/2.1, this more efficient scheme maps 128 bits of data to 132-bit blocks, significantly reducing protocol overhead to roughly 3% while maintaining transition density and frame framing.

3. Serialization (SerDes)

Inside the graphics processing unit or display controller, data is processed in wide parallel buses (such as 32-bit or 64-bit words) operating at relatively low clock frequencies to conserve power and manage timing constraints. The Serializer/Deserializer (SerDes) block takes these wide, parallel encoded symbols and shifts them out sequentially, bit-by-bit, onto a single serial channel. A high-frequency Phase-Locked Loop (PLL) generates the multi-gigahertz bit clocks required to drive this serialization, matching link rates that range from 1.62 Gbps (RBR) up to 20 Gbps (UHBR 20) per physical lane.

4. Differential Signaling and Output Drivers

The serialized digital bitstream is fed into output drivers that convert the binary states into analog electrical levels using differential signaling, typically implemented via Current Mode Logic (CML).

Instead of referencing a single wire to ground, DisplayPort transmits data over a twisted pair carrying complementary signals (\(D+\) and \(D-\)):

  • When a logical '1' is transmitted, current is steered to make \(D+\) positive relative to \(D-\).
  • When a logical '0' is transmitted, current is steered in reverse, making \(D-\) positive relative to \(D+\).

This differential approach rejects common-mode noise, allows for smaller voltage swings (typically between 200 mV and 1200 mV peak-to-peak), and minimizes power consumption while enabling transition speeds measured in picoseconds.

5. Equalization and Pre-Emphasis

High-frequency signals encounter severe attenuation, dielectric losses, and skin-effect losses as they traverse circuit board traces and cables. To combat this high-frequency loss and reduce Inter-Symbol Interference (ISI), the transmitter PHY applies pre-emphasis and de-emphasis filtering. The driver boosts the high-frequency transitions (when a bit toggles state) relative to sustained bits (repeated 1s or 0s). This intentional distortion ensures that after passing through a lossy transmission line, the received signal at the sink device displays an open "eye diagram" with clear timing margins.

The transformation of digital logic into electrical waveforms is not static; it is negotiated dynamically through Link Training. Using the dedicated, lower-speed Auxiliary (AUX) channel, the transmitter and receiver communicate prior to active video transmission. The receiver analyzes test patterns generated by the PHY transmitter and requests specific adjustments to the drive current (voltage swing levels) and high-frequency boost (pre-emphasis levels). This closed-loop calibration ensures the PHY drives electrical signals at the exact strength required for the specific cable length and transmission medium in use.