DisplayPort PCB Differential Impedance Tolerances

The DisplayPort standard requires strict PCB trace layout controls to maintain signal integrity across its multi-gigabit differential data lanes. This article outlines the specific intra-pair differential impedance values, standard tolerances, and layout constraints established by the Video Electronics Standards Association (VESA) for DisplayPort physical layer compliance.

Nominal Differential Impedance and Standard Tolerances

The VESA DisplayPort Physical Layer (PHY) Compliance Standard specifies that all high-speed main link differential lanes—as well as the AUX channel—must be routed with a nominal differential impedance (\(Z_{diff}\)) of 100 \(\Omega\).

The standard tolerance allowance on printed circuit boards (PCBs) is:

  • Nominal Differential Impedance: 100 \(\Omega\)
  • Tolerance Window: \(\pm 10\%\) (acceptable range of 90 \(\Omega\) to 110 \(\Omega\))
  • Nominal Single-Ended (Odd-Mode) Impedance: 50 \(\Omega\) nominal (\(\pm 10\%\), acceptable range of 45 \(\Omega\) to 55 \(\Omega\))

For newer, ultra-high bit rate standards (UHBR 10, UHBR 13.5, and UHBR 20 under DisplayPort 2.0/2.1), designers typically aim for a tighter fabrication tolerance of \(\pm 5\%\) to \(\pm 8\%\) (92 \(\Omega\) to 108 \(\Omega\)). This tighter window accounts for severe high-frequency attenuation, return loss, and parasitic effects at frequencies reaching up to 10 GHz Nyquist.

Intra-Pair Geometry and Coupling

Intra-pair differential impedance depends on the uniform physical coupling between the positive (TX+/RX+) and negative (TX-/RX-) traces:

  • Uniform Spacing: The edge-to-edge spacing between the two conductors in a differential pair must remain consistent along the entire routing path. Any widening or narrowing of this spacing creates localized impedance discontinuities.
  • Continuous Reference Planes: The pair must be referenced to an uninterrupted, solid ground plane directly on the adjacent layer. Reference plane splits or routing across power domains causes immediate impedance spikes and common-mode conversion.
  • Tight vs. Loose Coupling: While DisplayPort supports both edge-coupled and loosely coupled lines provided the 100 \(\Omega\) target is met, tight coupling is preferred to ensure environmental noise couples equally into both conductors as common-mode noise, which is then rejected by the differential receiver.

Intra-Pair Length Matching and Phase Skew

Differential impedance balance relies heavily on phase symmetry. DisplayPort specifies strict intra-pair skew limits to prevent phase mismatch from degrading the differential impedance profile:

  • Skew Limit: Intra-pair skew must generally not exceed 2 ps to 5 ps (depending on the transmission mode: RBR, HBR, HBR2, HBR3, or UHBR).
  • Length Matching: Traces within the same differential pair must be matched within a maximum tolerance of 5 mils (0.127 mm), with high-data-rate designs often targeting under 2 mils (0.05 mm).
  • Compensation Placement: When serpentine delay bends are required to match trace lengths, the compensation must occur as close to the point of divergence (such as an unavoidable bend or component breakout) as possible.

Discontinuity Management and Compliance Verification

VESA compliance testing validates impedance specifications using Time-Domain Reflectometry (TDR) with a defined signal rise time (typically around 130 ps for standard HBR or faster for HBR3/UHBR).

To ensure PCB traces pass TDR validation:

  • Via Transitions: Signal vias introduce capacitive discontinuities. When changing layers, GND stitching vias must be placed adjacent to the signal vias to preserve the 100 \(\Omega\) return current path.
  • Anti-Pads: Ground planes beneath AC-coupling capacitors (0402 or 0201 packages) and connector surface-mount pads must feature cutouts (anti-pads) to offset the capacitive impedance drop and keep the localized impedance within the 90–110 \(\Omega\) boundary.