DisplayPort Mvid and Nvid Time-Stamp Values Explained

In DisplayPort architecture, the video pixel clock and the high-speed link symbol clock operate asynchronously. To accurately reconstruct the original pixel clock at the receiving display, the transmitter calculates and sends two timing parameters: \(M_{vid}\) (Video Time-Stamp) and \(N_{vid}\). This article details how these values enable pixel clock recovery, maintain stream synchronization, and prevent buffer overruns or underruns during video stream synthesis.

The Purpose of Asynchronous Clocking

Unlike legacy display interfaces like DVI or HDMI, which traditionally transmit a dedicated physical clock line alongside data lines, DisplayPort relies on packetized data transmitted over fixed-rate serial lanes (such as 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, or 8.1 Gbps).

Because the native pixel rate of a given video resolution rarely matches the fixed frequency of the DisplayPort Main Link, the transmitter (source) and receiver (sink) operate on decoupled clock domains. The source must provide a mechanism for the sink to accurately synthesize the exact stream pixel clock (\(f_{pixel}\)) from the high-speed link symbol clock (\(f_{LS\_CLK}\)). This mechanism relies entirely on the \(M_{vid}\) and \(N_{vid}\) values.

The Clock Regeneration Formula

The relationship between the link symbol clock and the video pixel clock is represented as a rational fraction:

\[f_{pixel} = \left(\frac{M_{vid}}{N_{vid}}\right) \times f_{LS\_CLK}\]

  • \(f_{pixel}\): The original pixel clock frequency used by the video raster engine.
  • \(f_{LS\_CLK}\): The link symbol clock frequency derived from the transceiver link rate (Link Rate divided by 10 for 8b/10b encoding, or divided by 32 for 128b/132b encoding).
  • \(M_{vid}\): A dynamically measured counter representing the number of pixel clock cycles relative to a fixed measurement window.
  • \(N_{vid}\): A reference divider specifying the length of the link symbol clock measurement window.

How the Source Generates \(M_{vid}\) and \(N_{vid}\)

  1. Window Establishment (\(N_{vid}\)): The DisplayPort source sets a cycle count window based on the link clock. In asynchronous clock mode, \(N_{vid}\) is typically fixed to a standard power of two (such as \(2^{15} = 32,768\)) to simplify hardware division circuits.
  2. Cycle Counting (\(M_{vid}\)): Over the duration of \(N_{vid}\) cycles of the link clock, the source counts the elapsed number of pixel clock cycles. The resulting count is the \(M_{vid}\) value.
  3. Transmission in MSA: The source inserts the \(M_{vid}\) and \(N_{vid}\) values into the Main Stream Attribute (MSA) packets. These packets are transmitted during the vertical blanking intervals of the video stream.

Pixel Clock Synthesis at the Sink

Upon receiving the MSA packet, the sink extracts \(M_{vid}\) and \(N_{vid}\) and feeds them into an onboard digital Phase-Locked Loop (PLL) or clock synthesizer.

The sink multiplies its local link clock by \(M_{vid}\) and divides it by \(N_{vid}\). This recreates the exact original pixel clock frequency in phase and frequency. The synthesized clock then drives the internal display timing controller (TCON) and unloads pixel data from the receiver's elastic input buffer at the precise rate it was encoded.

Modes: Synchronous vs. Asynchronous

DisplayPort supports two modes for determining these values:

  • Synchronous Clock Mode: If the source can derive the pixel clock directly as an integer multiple or sub-multiple of the link clock, \(M_{vid}\) and \(N_{vid}\) remain completely static. This allows for simplified PLL tracking and low jitter.
  • Asynchronous Clock Mode: When the pixel clock and link clock originate from separate, independent oscillators (e.g., a discrete graphics card driving an external panel), the exact ratio fluctuates slightly over time due to clock drift and spread-spectrum clocking (SSC). In this mode, the source continuously recalculates \(M_{vid}\) and updates it in subsequent MSA packets so the sink PLL can track dynamic frequency shifts.

Why Accurate Time-Stamping is Critical

Without valid \(M_{vid}\) and \(N_{vid}\) values, the sink device cannot determine how fast to read data out of its FIFOs. A synthesized clock that runs even slightly too fast will cause buffer underflow (screen tearing or black frames), while a clock running too slow will cause buffer overflow and dropped frames. Together, \(M_{vid}\) and \(N_{vid}\) ensure seamless visual playback across disparate hardware clock domains.