DisplayPort Main Link Framing and Control Primitives

This article examines the specialized framing and control primitives that govern data transmission across the DisplayPort Main Link. To transport pixel data, audio streams, and ancillary metadata synchronously across multiple AC-coupled differential lanes, DisplayPort relies on deterministic framing symbols to delineate active data from blanking intervals. Below, we detail the primary control primitives, special characters, and framing structures utilized across both legacy 8b/10b systems and newer 128b/132b architectures.

8b/10b Control Primitives (Special Characters)

In DisplayPort versions 1.0 through 1.4a, the Main Link employs standard ANSI 8b/10b line coding. While data bytes are encoded into 10-bit symbols designated as D-codes, link control, boundary framing, and clock synchronization are handled by 12 designated special control symbols known as K-codes.

The primary primitives defined in the standard include:

  • Blanking Start (BS): Represented by the symbol K28.5. The BS primitive explicitly marks the end of active video pixel transmission and the beginning of the horizontal or vertical blanking interval.
  • Blanking End (BE): Represented by the symbol K27.7. The BE primitive indicates the conclusion of the blanking interval, signaling to the receiver that valid active video data follows immediately on the next clock cycle.
  • Fill Start (FS): Represented by the symbol K28.2. FS signals the start of dummy or stuffing data during periods where active bandwidth is lower than the link capacity, preventing FIFO underruns.
  • Fill End (FE): Represented by the symbol K29.7. FE demarcates the conclusion of the stuffing data sequence.
  • Secondary-data Start (SS): Represented by the symbol K28.2. The SS primitive indicates the arrival of secondary data packets, such as audio packets, InfoFrames, or high-dynamic-range (HDR) dynamic metadata, which are multiplexed during blanking intervals.
  • Secondary-data End (SE): Represented by the symbol K29.7. SE denotes the termination of a secondary data packet burst.
  • Scrambler Reset (SR): Represented by the symbol K28.5. To prevent electromagnetic interference (EMI), data is scrambled using a Linear Feedback Shift Register (LFSR). The SR primitive replaces the standard BS symbol once every 512th occurrence (and during link training) to force both the transmitter and receiver LFSR engines to reset to a known state (0xFFFF).

Before active framing commences, specific primitives configure and align the physical lanes. DisplayPort establishes link integrity through dedicated Training Pattern Sequences:

  • TPS1 (Training Pattern Sequence 1): Composed of alternating D10.2 symbols (0101010101), creating a square wave used by the sink device for clock recovery and phase locking.
  • TPS2 (Training Pattern Sequence 2): Implements a pseudo-random sequence punctuated by K28.5 control symbols to enable channel equalization, inter-lane deskew alignment, and symbol lock.
  • TPS3 / TPS4: Advanced training sequences utilized in DP 1.2 and DP 1.4 (HBR2/HBR3 speeds) providing deeper pseudo-random binary sequence patterns (PRBS7 and PRBS9) to mitigate complex inter-symbol interference (ISI) and optimize adaptive equalizer taps without relying solely on simple K-codes.

Multi-Stream Transport (MST) Framing

When utilizing Multi-Stream Transport (MST) to drive multiple independent displays through a single Main Link, framing shifts to a time-division multiplexed scheme:

  • MTP (Master Transfer Packet): The link transfers data in fixed 64-time-slot structures called Master Transfer Units (MTUs).
  • MTP Header Primitive: Specific control symbols designate the boundary of each MTP. A BS or SR primitive acts as the start of an MTP frame, followed by slot allocation indicators that map which stream owns which subsequent time slot.

128b/132b UHBR Framing Primitives

With DisplayPort 2.0/2.1 and the introduction of Ultra-High Bit Rate (UHBR) modes (UHBR10, UHBR13.5, and UHBR20), the physical layer shifts from 8b/10b to a more bandwidth-efficient 128b/132b line code.

Because K-codes are distinct to 8b/10b systems, 128b/132b systems replace them with dedicated control framing blocks:

  • 2-Bit Sync Headers: Every 132-bit block begins with a 2-bit synchronization header. 01b denotes a data block, while 10b designates a control block.
  • Link Training Symbols: Dedicated 132-bit blocks (e.g., TPS128) provide scrambled PRBS sequences for clock recovery and equalization.
  • Control Tokens: Control primitives such as Blanking Start, Blanking End, and Secondary Data indications are mapped as structured, multi-byte payload tokens nested inside designated 128b/132b control blocks, protected by forward error correction (FEC) parity bytes rather than standalone 10-bit symbols.