DisplayPort Link Training Equalization Phase Explained

During the DisplayPort link training sequence, the Equalization (EQ) Phase optimizes high-frequency signal integrity and establishes symbol synchronization across all active lanes. Following successful clock recovery, the transmitting Source and receiving Sink collaborate through the AUX channel to mitigate channel impairments such as high-frequency attenuation, jitter, and inter-symbol interference (ISI). This article details the mechanics, pattern transmissions, DPCD register interactions, and exit conditions that define the Equalization Phase.

Purpose of the Equalization Phase

While the preceding Clock Recovery phase ensures the receiver's Phase-Locked Loop (PLL) locks onto the incoming data stream's frequency and phase, it does not guarantee that data symbols are readable. The Equalization Phase addresses channel degradation caused by physical trace lengths, connectors, and cable quality. Its primary goals are to:

  • Optimize transmitter voltage swing and pre-emphasis settings.
  • Optimize receiver continuous-time linear equalization (CTLE) and decision feedback equalization (DFE).
  • Achieve symbol lock (character alignment) on every lane.
  • Compensate for lane-to-lane skew (inter-lane alignment).

The Equalization Process Step-by-Step

1. Transmission of Equalization Training Patterns

Once the Source confirms that all active lanes have achieved Clock Recovery, it immediately transitions to sending specialized training patterns:

  • TPS2 (Training Pattern Sequence 2): Used in DisplayPort 1.1a/1.2 for 8b/10b encoding to settle receiver equalizers and achieve symbol lock.
  • TPS3: Introduced in DisplayPort 1.2 for HBR2 link rates to address more severe channel losses.
  • TPS4: Introduced in DisplayPort 1.4 for HBR3 and higher rates, providing rich frequency content for complex receiver equalizers.
  • 128b/132b EQ Patterns: In DisplayPort 2.1 (UHBR modes), specific sequence blocks train both transmitter feed-forward equalization (FFE) and receiver equalizers.

2. Sink Signal Assessment

The Sink evaluates the incoming training pattern to determine whether the eye diagram is sufficiently open for error-free data recovery. The receiver attempts three milestones:

  • Channel Equalization: Ensuring the equalized signal meets threshold requirements.
  • Symbol Lock: Identifying symbol boundaries within the deserialized bitstream.
  • Inter-Lane Alignment: Realigning data across multi-lane configurations to remove propagation delay differences.

3. AUX Channel Negotiation Loop

Equalization is an iterative closed-loop process conducted via the bidirectional AUX channel:

  1. Source Transmits: The Source sends the selected training pattern at its current drive levels.
  2. Sink Analyzes: The Sink checks the signal quality and writes status flags to the DPCD (DisplayPort Configuration Data) memory map.
  3. Source Polls DPCD: After waiting a standardized interval (typically 400 microseconds for standard rates), the Source reads the DPCD registers (specifically LANE0_1_STATUS, LANE2_3_STATUS, and LANE_ALIGN_STATUS_UPDATED).
  4. Drive Parameter Adjustments: If equalization is incomplete, the Sink requests adjustments to the transmitter's voltage swing and pre-emphasis levels via DPCD registers (ADJUST_REQUEST_LANEx_y). The Source applies these requested levels and retransmits.

Phase Completion and Failure Modes

The Equalization Phase concludes in one of two ways:

  • Success: The Source reads that all active lanes have set LANEx_CHANNEL_EQ_DONE, LANEx_SYMBOL_LOCKED, and INTERLANE_ALIGN_DONE to 1. The Source then exits link training, switches from the training pattern to normal pixel stream transmission, and begins sending video and audio payload data.
  • Failure/Downshifting: The negotiation loop permits a maximum of five iterations at a given configuration. If the receiver cannot achieve equalization, symbol lock, or lane alignment within this limit—or if the drive settings reach their maximum allowable levels without success—the phase fails. The Source terminates the sequence, reduces the link rate (e.g., downshifting from HBR3 to HBR2) or lane count, and restarts link training from the Clock Recovery phase.