DisplayPort Link Retraining Error Thresholds

This article provides an overview of the error rate conditions and thresholds that trigger a link retraining sequence in DisplayPort interfaces. It examines the symbol error rate monitoring mechanisms defined by the VESA DisplayPort standard, the Bit Error Rate (BER) baseline requirements, and how the sink device signals the source device via the Hot Plug Detect (HPD) pin to initiate retraining.

In the DisplayPort specification, link retraining is primarily governed by the target Bit Error Rate (BER) and the sink device’s ability to maintain physical layer synchronization. For legacy 8b/10b encoding (RBR, HBR, HBR2, and HBR3 link rates), the standard requires an operational BER of less than or equal to \(10^{-9}\). A BER exceeding \(10^{-9}\) corresponds roughly to a Symbol Error Rate (SER) greater than \(10^{-8}\). When link degradation causes errors to surpass this threshold, the sink device triggers a retraining sequence to restore signal integrity or negotiate a lower link rate.

In modern DisplayPort revisions utilizing 128b/132b channel encoding (such as UHBR links in DisplayPort 2.1) alongside Forward Error Correction (FEC), the threshold model is split. The pre-FEC raw BER must typically stay below \(10^{-4}\) to allow FEC logic to function properly, while the post-FEC target is maintained at a BER of \(10^{-12}\). If uncorrectable FEC blocks occur consistently or if the raw symbol error rate overwhelms the decoder beyond these operating margins, retraining is initiated.

Link monitoring is handled directly by the sink device using DisplayPort Configuration Data (DPCD) registers. The sink continuously monitors the incoming bitstream and updates error parameters within the SYMBOL_ERROR_COUNT_LANE registers (addresses 00210h through 00217h). These 15-bit registers accumulate symbol errors over defined measurement intervals. When the counter reaches its saturation limit or calculates an error density higher than the specified BER allowance, the link is considered compromised.

In addition to accumulated symbol errors, instantaneous triggers cause an immediate link retraining request without waiting for error rate calculations. These immediate triggers include:

• Loss of Clock Recovery (CR) on any active lane.
• Loss of Channel Equalization (EQ) or Symbol Lock (SYMBOL_LOCKED = 0).
• Loss of Inter-Lane Alignment (INTERLANE_ALIGN_DONE = 0).

Once the error rate threshold is crossed or symbol lock is lost, the sink asserts an interrupt request by pulsing the Hot Plug Detect line low for a duration between 0.5 ms and 1.0 ms (HPD_IRQ). Upon detecting the pulse, the source device reads the DPCD link status registers (addresses 00200h to 0020Ch) to verify the failure mode. Finding that the symbol error count has exceeded the threshold or that synchronization has dropped, the source halts standard data transmission and re-executes the link training protocol across all active lanes.