DisplayPort Intra-Pair Skew and Length Matching

High-speed digital interfaces like DisplayPort rely on differential signaling to transmit massive amounts of video data with minimal noise. Intra-pair skew occurs when the two complementary signals in a differential pair arrive at the receiver at slightly different times due to physical propagation delays. To maintain signal integrity, minimize electromagnetic interference, and prevent data corruption at multi-gigabit speeds, printed circuit board (PCB) designers must strictly match the lengths of the traces within each DisplayPort lane.

Understanding Intra-Pair Skew

DisplayPort uses differential signaling, where data is transmitted over a pair of closely coupled conductors carrying equal and opposite voltage swings (positive and negative polarities). The receiver decodes the data by measuring the voltage difference between the two traces rather than measuring a single trace against a ground reference.

Intra-pair skew is the time difference (or phase offset) between the true and complementary signals of that single differential pair. While inter-pair skew refers to timing differences between distinct lanes, intra-pair skew refers specifically to the delay between the two lines that make up one single lane. This skew is typically measured in picoseconds (ps) or millimeters/mils of trace length mismatch.

Causes of Intra-Pair Skew

Intra-pair skew is primarily caused by geometric and material asymmetries in the PCB layout:

  • Trace Length Differences: Unequal routing paths, especially around corners, bends, or obstacles like vias and component pads, cause one trace to be physically longer than the other.
  • The Fiber Weave Effect: The dielectric core of a PCB is woven fiberglass encased in resin. Glass and resin have different dielectric constants (\(\epsilon_r\)). If one trace runs primarily over fiberglass bundles while the other runs over resin-rich gaps, signals travel at different speeds even if the traces are geometrically identical in length.

Why DisplayPort Demands Precise Length Matching

DisplayPort standards—ranging from HBR (2.7 Gbps) to UHBR 20 (20 Gbps per lane in DisplayPort 2.0/2.1)—operate at extremely high frequencies with picosecond-level unit intervals (UI). At these data rates, even a minute difference in trace length causes significant signal degradation.

1. Preventing Eye Diagram Closure

As data rates increase, the time window in which a bit can be reliably sampled (the eye opening) shrinks. When intra-pair skew occurs, the rising and falling edges of the differential signals misalign. This phase difference reduces the differential amplitude, slows the effective edge rate, and increases jitter. The resulting degradation closes the eye diagram at the receiver, causing bit errors, link-training failures, or complete loss of video output.

2. Minimizing Common-Mode Noise and EMI

In an ideal differential pair, the equal and opposite currents cancel out radiation, and the sum of the voltages equals zero. When intra-pair skew is present, this cancellation breaks down. The phase mismatch converts a portion of the differential-mode signal into common-mode noise. Common-mode voltage radiates efficiently off the PCB, cables, and connectors, often causing the system to fail regulatory electromagnetic compatibility (EMC) and EMI tests.

3. Ensuring Accurate Receiver Threshold Crossing

A differential receiver detects transitions at the exact moment the positive and negative signals cross each other. If one signal is delayed, the zero-crossing point shifts in time, directly translating into duty-cycle distortion and deterministic jitter that downstream clock and data recovery (CDR) circuits may fail to compensate for.

Implementation Guidelines for PCB Designers

To prevent intra-pair skew from compromising DisplayPort performance, designers adhere to strict layout constraints:

  • Tight Length Tolerances: For modern DisplayPort rates (such as HBR3 or UHBR), intra-pair trace lengths are typically matched within 0.1 mm (approximately 4 to 5 mils), corresponding to less than 1 to 2 picoseconds of skew.
  • Compensate Close to the Source: Length tuning (such as serpentine or trombone routing) should be applied immediately adjacent to the point where the mismatch occurs, such as right after a bend or a breakout area. Delaying compensation allows common-mode noise to propagate along the mismatched segment.
  • Fiber Weave Mitigation: Routing traces at an angle relative to the PCB weave (e.g., a 10° to 45° zigzag or bias) or using tightly woven glass fabrics (like 1067 or 1078 glass styles) ensures both traces in a pair encounter uniform dielectric properties.