DisplayPort Eye Diagram Capture on High-Bandwidth DSOs

Compliance validation for DisplayPort interfaces requires validating signal integrity against strict VESA physical layer specifications. High-bandwidth digital storage oscilloscopes (DSOs) capture DisplayPort eye diagrams by utilizing high-fidelity probe fixtures, sampling ultra-high-speed differential signals, applying standardized software Clock Data Recovery (CDR), and emulating reference receiver equalization to overlay data transitions into a validated eye mask.

1. Test Fixture Setup and Signal Routing

DisplayPort transmitters use AC-coupled, differential signaling across multiple main link lanes. To capture these signals without introducing impedance mismatches or excessive attenuation:

  • Compliance Test Fixtures: The device under test (DUT) connects to a standardized VESA test fixture that breaks out the high-speed differential pairs (Main Link Lanes 0 through 3) into high-bandwidth RF coaxial connectors (typically 2.92 mm or 2.4 mm).
  • AUX Channel Handshaking: The AUX channel is routed to control hardware or an auxiliary oscilloscope channel to drive the transmitter into compliance test patterns, such as PRBS7, PRBS15, or standardized compliance patterns (CP0 through CP20 for newer UHBR standards).
  • Direct Coaxial Input: The signals are routed directly to 50-ohm oscilloscope inputs via phase-matched coaxial cables, bypassing active probes to maximize bandwidth and minimize channel skew.

2. High-Bandwidth Real-Time Acquisition

Capturing the high-frequency harmonics of DisplayPort signals requires an oscilloscope with sufficient analog bandwidth and sample rate:

  • Bandwidth Sizing: For DisplayPort 1.4 (HBR3 at 8.1 Gbps), a minimum oscilloscope bandwidth of 13 GHz to 16 GHz is required. For DisplayPort 2.1 (UHBR10, UHBR13.5, and UHBR20 running up to 20 Gbps per lane), bandwidths between 25 GHz and 50 GHz are necessary to capture the 3rd or 5th harmonics.
  • Sampling Rate: The oscilloscope operates at high sampling rates (typically 40 GS/s to 128 GS/s) to maintain adequate points per unit interval (UI), ensuring accurate timing and low jitter noise floor.

3. Software Clock Data Recovery (CDR)

DisplayPort does not transmit an explicit clock signal along with the high-speed data; the clock is embedded in the serial bit stream.

  • The oscilloscope captures long continuous records of the serial data stream into its acquisition memory.
  • Post-processing algorithms apply a standardized software Phase-Locked Loop (PLL) model defined by the VESA specification. For example, DisplayPort uses a specific Type-2/Type-3 golden PLL tracking bandwidth (such as a 10 MHz or 20 MHz loop bandwidth) to track low-frequency jitter while exposing high-frequency jitter in the eye diagram.

4. Reference Equalization Emulation

Modern DisplayPort standards rely heavily on receiver equalization to open closed eye diagrams caused by transmission line losses.

  • High-bandwidth oscilloscopes execute digital signal processing (DSP) to simulate the worst-case VESA reference receiver model.
  • Continuous Time Linear Equalization (CTLE): The software filters apply prescribed frequency-peaking curves to compensate for high-frequency channel loss.
  • Decision Feedback Equalization (DFE): For UHBR rates, the software applies multi-tap DFE algorithms to subtract inter-symbol interference (ISI) from the sampled signal.

5. Eye Diagram Rendering and Mask Compliance Testing

Once CDR and equalization models process the acquired waveform:

  • The oscilloscope segments the continuous record into single unit intervals based on the recovered clock edges.
  • These intervals are folded and overlaid onto a persistence grid to render the final eye diagram.
  • Automated compliance software applies the standardized VESA compliance mask onto the center of the eye.
  • The system evaluates parameters including Eye Height (EH), Eye Width (EW), Total Jitter (TJ), Random Jitter (RJ), and Deterministic Jitter (DJ). If any waveform transition intersects the polygon-shaped keep-out zone of the mask, the lane fails compliance validation.