DisplayPort DPCD Registers for Link Rate and Lane Count

When a DisplayPort source, such as a GPU, connects to a display device, it reads the DisplayPort Configuration Data (DPCD) over the Auxiliary (AUX) channel to negotiate connection parameters. This article identifies the specific DPCD register addresses used by the display to report its maximum supported link rate and lane count to the graphics card, explaining their bit definitions and values during link training.

The DPCD Receiver Capability Field

The DPCD address space begins with the Receiver Capability field, spanning addresses 00000h to 000FFh. This read-only block informs the GPU of the sink device’s hardware capabilities prior to link training. Two primary registers within this block define the maximum throughput limits of the physical link.

The maximum supported link rate is reported at DPCD address 00001h (MAX_LINK_RATE).

The GPU reads the byte stored at this address to determine the highest bandwidth frequency the monitor can accept per lane:

  • 06h (RBR): Reduced Bit Rate, operating at 1.62 Gbps per lane.
  • 0Ah (HBR): High Bit Rate, operating at 2.70 Gbps per lane.
  • 14h (HBR2): High Bit Rate 2, operating at 5.40 Gbps per lane.
  • 1Eh (HBR3): High Bit Rate 3, operating at 8.10 Gbps per lane.

If bit 7 of register 0000Eh (TRAINING_AUX_RD_INTERVAL) is set to 1, the source must check the Extended Receiver Capability field starting at 02200h. In this scenario, the primary link rate register shifts to address 02201h. For DisplayPort 2.0/2.1 Ultra-High Bit Rate (UHBR) modes, higher link rates—UHBR10 (10 Gbps), UHBR13.5 (13.5 Gbps), and UHBR20 (20 Gbps)—are additionally defined through registers 02215h (13.5_GBPS_SUPPORT) and 00001h/02201h encoding sets.

Maximum Lane Count Register: Address 00002h

The maximum number of physical data lanes supported by the monitor is defined at DPCD address 00002h (MAX_LANE_COUNT).

The register byte provides the following specific bit allocations:

  • Bits [4:0] (MAX_LANE_COUNT): Specifies the maximum number of main link lanes supported by the receiver. Standard valid values are:
    • 01h: 1 lane
    • 02h: 2 lanes
    • 04h: 4 lanes
  • Bit 5 (TPS3_SUPPORTED): Indicates support for Training Pattern Sequence 3 (used for HBR2 capabilities).
  • Bit 6 (ENHANCED_FRAME_CAP): Indicates support for Enhanced Framing mode.
  • Bit 7 (TPS4_SUPPORTED): Indicates support for Training Pattern Sequence 4 (used for HBR3 capabilities).

If the Extended Receiver Capability field is activated, address 02202h mirrors this register to define the maximum lane count under extended profiles.

Summary of Operation

During the connection handshake:

  1. The GPU reads address 00001h (or 02201h) to establish the frequency cap.
  2. The GPU reads address 00002h (or 02202h) to determine whether 1, 2, or 4 lanes are available.
  3. The GPU configures its link training sequence, attempting connection at the optimal combination of these values.