DisplayPort Differential Receiver Voltage Envelope

This article provides an overview of how the VESA DisplayPort specification defines the allowable voltage envelope for differential receivers across its Main Link physical layer. It covers the core electrical parameters governing receiver compliance, including AC coupling requirements, peak-to-peak differential voltage tolerances, common-mode operating limits, absolute maximum ratings, and eye-mask boundaries required for signal integrity.

AC Coupling and DC Isolation

The DisplayPort physical layer relies on mandatory AC coupling capacitors integrated into the differential pairs of the Main Link. These capacitors isolate the DC bias levels of the transmitter from the receiver. Because direct current cannot pass between the devices, the receiver does not need to accept the transmitter’s DC operating point. Instead, the DisplayPort specification requires the receiver to establish its own internal DC common-mode voltage (\(V_{RX-DC-CM}\)), typically biased via internal terminations referenced to an internal ground or power rail.

Differential Input Voltage Swing

The specification establishes both minimum and maximum limits on the differential signal amplitude that a receiver must tolerate:

  • Minimum Differential Voltage (\(V_{RX-DIFFp-p}\)): A compliant receiver must accurately decode signals with small differential amplitudes after cable attenuation and channel loss. Depending on the link rate (e.g., RBR, HBR, HBR2, HBR3, and UHBR), the minimum eye height post-equalization typically scales down to between 90 mV and 120 mV peak-to-peak differential.
  • Maximum Differential Voltage: The receiver must tolerate maximum transmit swings without saturating or incurring damage. DisplayPort specifies a maximum input differential swing of up to 1200 mV to 1380 mV peak-to-peak differential, accommodating signals originating from short, low-loss interconnects operating at maximum drive levels.

Common-Mode Voltage Limits

Because AC coupling blocks direct DC common-mode transmission, the receiver's common-mode specifications focus on self-biasing and dynamic fluctuations:

  • DC Common-Mode Range (\(V_{RX-DC-CM}\)): The internal termination network establishes the DC operating point. Receivers commonly utilize a termination scheme tied to a known voltage rail (such as 0 V or a dedicated termination supply), keeping the nominal bias stable.
  • AC Common-Mode Noise (\(V_{RX-CM-AC-p-p}\)): Due to trace asymmetries, driver imbalances, and external electromagnetic interference, high-frequency common-mode noise can couple into the differential pair. The specification defines an upper threshold for tolerable peak-to-peak AC common-mode voltage—often limited to roughly 50 mV to 100 mV peak-to-peak—ensuring that common-mode variations do not degrade differential detection or cause common-mode to differential conversion.

Absolute Single-Ended Voltage Ratings

To prevent hardware damage and electrostatic overstress, the specification sets absolute boundaries for single-ended voltages applied to the receiver's positive and negative input pins (\(RX_p\) and \(RX_n\)). Referenced to the receiver's ground plane, the allowable single-ended voltage envelope generally falls within a specified window (typically between -0.4 V and roughly 2.0 V to 3.6 V, depending on the DisplayPort revision and silicon process geometry). Voltages falling outside this range exceed the receiver's protective diode thresholds and operational tolerances.

Dynamic Eye Mask and Equalization Constraints

The dynamic allowable voltage envelope is formally verified at designated compliance test points:

  • Test Points (TP3 and TP4): TP3 represents the signal as it arrives at the receiver connector pins, while TP4 represents the signal at the internal receiver die.
  • Equalization Processing (TP4_EQ): For higher bit rates (such as HBR3 and UHBR), inter-symbol interference (ISI) typically closes the physical eye at the connector. The specification incorporates a reference Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE) behavioral model. The allowable voltage envelope is defined by a diamond- or hexagonal-shaped eye mask applied after this reference equalization.
  • Eye Height Boundaries: The receiver must maintain an open voltage eye margin centered within this mask, satisfying specified Bit Error Ratio (BER) targets (typically \(1 \times 10^{-9}\) or better for older standards, and \(1 \times 10^{-12}\) for modern ultra-high bit rates) to be considered compliant.