DisplayPort Differential Impedance Standards

This article provides an overview of the characteristic impedance specifications required for DisplayPort differential signal pairs. It details the nominal differential and single-ended values established by the Video Electronics Standards Association (VESA), explains the standard design tolerances, and outlines essential PCB layout considerations to maintain signal integrity across high-speed lanes.

Standard Impedance Values

According to VESA specifications, the standard nominal characteristic impedance for DisplayPort differential signal pairs is 100 Ω (ohms).

Because differential signaling relies on two complementary conductors (the positive and negative lines), the impedance can be measured in two ways:

  • Differential Impedance (\(Z_{diff}\)): 100 Ω nominal between the positive and negative traces.
  • Single-Ended (Odd-Mode) Impedance (\(Z_0\)): 50 Ω nominal for each individual conductor relative to the reference ground plane.

This 100 Ω requirement applies to the high-speed Main Link lanes (which carry video and audio data) as well as the bidirectional Auxiliary (AUX) Channel.

Design Tolerances

While the nominal target is 100 Ω, manufacturing variations in printed circuit boards (PCBs) and cable assemblies necessitate standard tolerances:

  • PCB Traces: A tolerance of ±10% is standard for board layout, establishing an acceptable differential impedance window of 90 Ω to 110 Ω.
  • Cable Assemblies: VESA compliance testing specifies strict return loss and time-domain reflectometry (TDR) parameters. The cable impedance must stay within roughly 100 Ω ± 10% to pass certification, preventing significant signal degradation over longer distances.

Why 100-Ohm Impedance Matching Matters

DisplayPort operates at very high transmission speeds, ranging from Reduced Bit Rate (RBR at 1.62 Gbps per lane) up to Ultra High Bit Rate (UHBR 20 at 20 Gbps per lane in DisplayPort 2.1).

At these frequencies, any deviation from the 100 Ω standard introduces impedance discontinuities. These mismatches cause:

  • Signal Reflections: Energy bounces back toward the transmitter, causing amplitude distortion and noise.
  • Increased Jitter: Distorted edge transitions reduce the timing margin at the receiver.
  • Eye Closure: Reflections and attenuation degrade the differential eye diagram, leading to bit errors or complete link failure.

PCB Layout Rules for DisplayPort Traces

To achieve and maintain a consistent 100 Ω differential impedance across a board:

  1. Controlled Dielectric Spacing: Calculate trace width and pair separation using the PCB stackup's specific dielectric constant (\(D_k\)) to hit exactly 100 Ω differential.
  2. Continuous Reference Planes: Route all differential pairs over solid, uninterrupted ground planes. Never route high-speed DisplayPort pairs across plane splits or voids.
  3. Intra-Pair Length Matching: Keep the positive and negative traces within a pair tightly matched in length (typically within 5 mils or 0.127 mm) to prevent skew and common-mode noise.
  4. Minimize Layer Transitions: Keep pairs on the same signal layer as much as possible. When vias are unavoidable, place ground return vias immediately adjacent to the signal vias to provide a continuous return path.