DisplayPort Clock Recovery Link Training Explained

During DisplayPort initialization, Clock Recovery (CR) is the crucial first phase of link training that establishes a synchronized bit clock between the transmitter (Source) and the receiver (Sink). This process ensures the Sink's Clock and Data Recovery (CDR) circuitry can reliably lock onto the incoming high-speed serial data stream before signal equalization begins. By iteratively transmitting dedicated training patterns and exchanging status feedback over the bi-directional Auxiliary (AUX) Channel, the two devices dynamically adjust voltage swing and pre-emphasis levels across all active lanes until an optimal, jitter-tolerant electrical connection is established.

The Purpose of Clock Recovery

Modern DisplayPort interfaces operate without a dedicated physical clock line. Instead, the clock signal is embedded directly within the 8b/10b- or 128b/132b-encoded data stream. For the Sink to decode pixels and control packets accurately, its internal Phase-Locked Loop (PLL) must reconstruct the transmit clock. Clock Recovery link training resolves physical signal degradation—caused by trace routing, connectors, and cable quality—by calibrating the signal's electrical parameters until the CDR can continuously track the phase and frequency of the incoming data.

Step 1: Capability Discovery and Setup

Before transmitting high-speed training signals, the Source reads the Sink's capabilities by accessing the DisplayPort Configuration Data (DPCD) registers via the 1 Mbps Manchester-encoded AUX Channel.

  1. Querying Receiver Limits: The Source checks the Sink's maximum supported link rate (e.g., RBR, HBR, HBR2, HBR3, or UHBR) and lane count (1, 2, or 4 lanes).
  2. Establishing Initial Parameters: The Source selects the desired link rate and lane count, then programs the initial electrical drive parameters. Clock recovery typically begins at the lowest drive strength: Voltage Swing Level 0 and Pre-emphasis Level 0.

Step 2: Transmission of Training Pattern Sequence 1 (TPS1)

Once configured, the Source switches its high-speed main link lanes from idle to transmitting Training Pattern Sequence 1 (TPS1).

TPS1 consists of a repetitive, low-complexity bit sequence with dense transitions (such as alternating high and low states, D10.2 in 8b/10b encoding). This dense transition density provides rich edge information, allowing the Sink's CDR circuit to detect bit boundaries rapidly and align its internal clock with minimal pattern-dependent jitter.

Step 3: The AUX Feedback Loop

While TPS1 streams over the main link, a closed-loop negotiation occurs over the AUX Channel:

  • Sink Evaluation: The Sink checks whether its local PLL has achieved phase and frequency lock on each lane.
  • Status Reporting: The Sink updates specific DPCD registers—notably LANE0_1_STATUS and LANE2_3_STATUS—where a dedicated CR_DONE bit exists for each lane.
  • Source Polling: The Source reads the DPCD status registers at specified time intervals (typically 100 microseconds for standard link rates, shorter for UHBR rates).

Step 4: Iterative Signal Adjustment

If any lane fails to set its CR_DONE bit, the Sink calculates required drive adjustments and requests higher drive parameters via the DPCD ADJUST_REQUEST registers.

  1. Increasing Voltage Swing: The Sink normally requests an increment in voltage swing to boost signal amplitude and overcome channel attenuation.
  2. Source Adaptation: The Source updates its physical transmitter output settings to match the requested voltage swing or pre-emphasis levels and continues sending TPS1.
  3. Loop Constraints: The Source will repeat this adjustment process up to five consecutive times at the same voltage level, or until it reaches the maximum allowable voltage swing (Level 3).

Step 5: Transition or Fallback

Clock Recovery concludes in one of two ways:

  • Success: When the Source reads that all active lanes have asserted the CR_DONE bit simultaneously, the Clock Recovery phase succeeds. The transmitter immediately transitions to the second phase of link training: Channel Equalization (using TPS2, TPS3, or TPS4) to optimize inter-symbol interference (ISI) correction.
  • Failure and Downshifting: If the Source reaches the maximum voltage swing without all lanes achieving lock, or if the adjustment loop times out, Clock Recovery fails. The Source then drops down to a lower link rate (e.g., stepping down from HBR2 to HBR) or reduces the lane count, restarting the Clock Recovery phase from the beginning to find a stable operational mode.