DisplayPort 8b/10b Encoding Explained
This article provides an overview of the 8b/10b line encoding scheme utilized in DisplayPort standards up through DisplayPort 1.4. It examines the fundamental mechanics of mapping 8-bit data bytes to 10-bit transmission characters, explains why this physical-layer protocol is necessary for clock recovery and direct current (DC) balance, details the role of control symbols in link management, and highlights the resulting 20% bandwidth overhead that shaped DisplayPort's effective data throughput until the introduction of DisplayPort 2.0.
What Is 8b/10b Encoding?
Originally developed by IBM researchers Al Widmer and Peter Franaszek in 1983, 8b/10b encoding is a telecommunications line code that maps an 8-bit data byte (providing 256 possible data values) to a 10-bit symbol (providing 1,024 possible combinations). DisplayPort adopted this standard starting with DisplayPort 1.0 and continued utilizing it through versions 1.1, 1.2, 1.3, and 1.4 across all its legacy link rates: RBR (1.62 Gbps), HBR (2.7 Gbps), HBR2 (5.4 Gbps), and HBR3 (8.1 Gbps per lane).
The Primary Purposes in DisplayPort
The transmission of high-speed serial data over DisplayPort's differential pairs requires solving specific physical-layer transmission challenges. The 8b/10b scheme achieves three primary goals:
- Clock Recovery: High-speed DisplayPort lanes do not carry a dedicated physical clock line. Instead, the receiver extracts the clock signal directly from transitions in the serial data stream using a Clock and Data Recovery (CDR) circuit. The 8b/10b scheme ensures that long runs of consecutive identical bits (such as all zeros or all ones) never occur. By limiting maximum run length to no more than five identical bits, the receiver receives frequent signal transitions to maintain phase lock.
- DC Balance: DisplayPort uses AC-coupled differential signaling with capacitors inline on each lane. If a signal contains an unequal number of ones and zeros over time, a direct current (DC) voltage offset accumulates, causing signal degradation and baseline wander. 8b/10b maintains a continuous count called "Running Disparity" (RD). Every transmitted 10-bit symbol either has an equal number of ones and zeros (disparity zero) or has a disparity of \(+2\) or \(-2\). The transmitter alternates between positive and negative disparity representations to ensure the average DC bias across the transmission line remains zero.
- Error Detection and Framing: Because only 256 of the 1,024 available 10-bit patterns are needed for standard data symbols (referred to as D-codes), the remaining patterns allow for robust error handling. If a receiver encounters an unassigned 10-bit code or an invalid disparity jump, it immediately flags a transmission error. Furthermore, 12 specific non-data patterns (referred to as K-codes or special characters) are reserved for control functions, including frame delineation, blanking indicators, and the comma symbol (K28.5) used for physical lane alignment and training sequences.
Bandwidth Impact and Efficiency
The trade-off for the signal integrity provided by 8b/10b encoding is a fixed 20% bandwidth overhead. Because two extra bits are added to every eight bits of payload, the effective data throughput is always 80% of the raw physical signaling rate:
\[\text{Effective Throughput} = \text{Raw Bit Rate} \times \left(\frac{8}{10}\right)\]
For example, DisplayPort 1.4 running at its maximum HBR3 link rate operates at a raw rate of 8.1 Gbps per lane across 4 lanes, yielding a 32.4 Gbps raw link rate. After applying the 8b/10b encoding penalty, the maximum uncompressed payload throughput is reduced to 25.92 Gbps.
This 20% overhead became a limiting bottleneck as display resolutions reached 4K at high refresh rates and 8K. Consequently, VESA transitioned away from 8b/10b in DisplayPort 2.0 and 2.1, adopting a more efficient 128b/132b line encoding scheme that reduces physical-layer overhead to roughly 3%.