What Is an Unordered Access View (UAV) in DirectX?

An Unordered Access View (UAV) is a DirectX resource binding interface that grants GPU shaders the ability to read and write to memory buffers or textures simultaneously without adhering to a fixed execution order. Introduced in Direct3D 11 and foundational to Direct3D 12, UAVs bypass traditional graphics pipeline stages to facilitate general-purpose GPU computing, complex post-processing effects, and flexible data manipulation. This article explains what a UAV is, its role within the DirectX architecture, and the architectural mechanisms that enable concurrent read-write access without causing memory corruption.

Understanding the Role of a UAV

In the traditional DirectX graphics pipeline, resource access is strictly segregated to ensure predictable rasterization. Shaders read input data through Shader Resource Views (SRVs) and output results via Render Target Views (RTVs) or Depth Stencil Views (DSVs). These outputs are written sequentially to fixed locations corresponding to specific pixel or vertex coordinates.

A UAV removes these constraints. It acts as an adapter around a raw GPU resource—such as a 1D/2D/3D texture, a structured buffer, or a byte-address buffer—exposing it to the shader as an arbitrary read-write memory block. While UAVs are most commonly used in Compute Shaders, they can also be bound to Pixel Shaders to enable algorithms like Order-Independent Transparency (OIT) and custom software rasterization.

How a UAV Enables Concurrent Read-Write Access

Permitting hundreds or thousands of concurrent GPU threads to read and write to the same memory allocation introduces data hazards, race conditions, and cache incoherency. A UAV facilitates concurrent access through several key mechanisms:

1. Out-of-Order Memory Addressing

Unlike Render Target Views, which bind thread outputs strictly to output positions governed by the rasterizer, UAVs allow threads to read from or write to any index or coordinate within the underlying resource. Threads determine their access locations dynamically at runtime using computed thread IDs or data offsets. Because the access pattern is decoupled from thread execution order, the system is fundamentally "unordered."

2. Atomic Intrinsic Operations

Concurrent reads and writes to identical memory addresses cause race conditions. To resolve this, DirectX provides HLSL atomic operations (intrinsics beginning with Interlocked, such as InterlockedAdd, InterlockedMin, and InterlockedCompareExchange) for resources bound as UAVs.

When a thread performs an atomic operation via a UAV, the GPU's memory controller guarantees that the read-modify-write cycle completes as a single, uninterrupted transaction. This prevents concurrent threads from overwriting each other's data, enabling structures like thread-safe counters, append buffers, and linked lists.

3. Hardware Cache Coherency and Bypasses

Traditional pipeline reads rely heavily on texture caches optimized for spatial locality, while writes rely on dedicated output-merger write queues. Because UAVs perform both reads and writes:

  • The GPU routes UAV accesses through unified L1/L2 caches or directly to global device memory (VRAM).
  • When a write occurs, the corresponding cache lines are marked dirty or invalidated across active compute units, ensuring that subsequent reads observe the latest modified data.

4. Synchronization Barriers and Memory Fences

Because concurrent execution is non-deterministic, shaders use explicit barriers to manage access sequencing. Within a thread group, HLSL intrinsics like DeviceMemoryBarrier() or AllMemoryBarrierWithGroupSync() force all pending UAV writes to commit to memory before execution continues.

At the API level (especially in Direct3D 12), developers use resource barriers (such as D3D12_RESOURCE_BARRIER_TYPE_UAV) to notify the GPU driver that all preceding UAV write operations must complete before any subsequent work begins reading or writing that same resource.

Summary of Benefits and Trade-offs

By granting random-access memory capabilities to shaders, UAVs make advanced compute algorithms, physics simulations, and dynamic particle systems possible directly on the GPU. However, this flexibility shifts synchronization responsibility to the developer. Uncontrolled concurrent access without atomics or barriers can introduce race conditions and memory stalls, requiring deliberate memory layout and barrier management to maintain optimal hardware utilization.