Hardware Supporting Native DirectX 12 Work Graphs

DirectX 12 Work Graphs revolutionize GPU programming by allowing the graphics processor to autonomously generate and schedule its own tasks rather than relying on the CPU to manage command buffers. While early implementations or legacy chips rely on software emulation layers and compute loops running in driver space, modern graphics architectures feature dedicated hardware scheduling logic that can manage dynamic node expansion natively. This article breaks down the GPU architectures that provide native, hardware-level acceleration for DirectX 12 Work Graphs without falling back to CPU or driver-level compute emulation.

The Role of Native Hardware Scheduling in Work Graphs

In traditional GPU pipelines, dynamic workloads require indirect dispatches, round-trips to CPU memory, or complex driver-synthesized compute passes to allocate and dispatch work records. Native Work Graph execution requires the GPU’s hardware front-end, work distributor, and cache hierarchy to natively handle:

  • Dynamic memory allocation for graph nodes in on-chip or local memory.
  • Work record prioritization and queuing directly in silicon.
  • Autonomous generation and launch of subsequent grid workloads without host-driver injection.

When an architecture lacks this native capability, the DirectX 12 driver must synthesize compute shaders to emulate a software scheduler, adding latency and consuming extra memory bandwidth.

AMD RDNA 3 and RDNA 3.5

AMD's RDNA 3 architecture (found in Radeon RX 7000 series desktop GPUs and Radeon 700M series integrated graphics) was the primary launch platform for D3D12 Work Graphs. RDNA 3 natively accelerates Work Graphs directly on silicon via its revised Command Processor and Asynchronous Compute Engines (ACE).

  • Hardware Command Processor: RDNA 3 features an upgraded front-end capable of handling Work Graph execution queues directly in silicon. The command processor allocates execution space for nodes on the fly without waiting for driver-managed dispatch commands.
  • Decoupled Work Distribution: The compute units (CUs) can generate execution records into shared L2/Infinity Cache structures, which the hardware scheduler drains dynamically.
  • RDNA 3.5: Carries forward this native hardware pipeline into newer mobile and APU configurations (such as Strix Point), providing hardware-accelerated autonomous node dispatching.

NVIDIA Ada Lovelace and Ampere

NVIDIA supports DirectX 12 Work Graphs across both its Ampere (GeForce RTX 30 series) and Ada Lovelace (GeForce RTX 40 series) architectures, but Ada Lovelace features the most direct, silicon-level acceleration for the feature.

  • Ada Lovelace (RTX 40 Series): Ada includes an overhauled Work Distributor and a massive increase in Level 2 cache capacity. This allows parent nodes to write child-node records directly into fast, on-chip memory. The hardware scheduler reads these structures natively to launch subsequent thread groups, preventing global memory round-trips and completely bypassing host intervention.
  • Ampere (RTX 30 Series): Ampere features hardware execution management through its hardware work distributor that handles Work Graphs natively at the GPU command stream level. However, because of smaller L2 cache subsystems compared to Ada, record buffering relies more heavily on local VRAM bandwidth, though it still bypasses CPU driver emulation.

Intel Xe2 Architecture

Intel’s first-generation Xe-HPG (Alchemist / Arc A-Series) architecture handles advanced execution graphs primarily through driver-level compute emulation paths. However, Intel's Xe2 architecture (codenamed Battlemage and found in Lunar Lake integrated processors) natively addresses autonomous GPU dispatch.

  • Xe2 Hardware Schedulers: Xe2 incorporates dedicated hardware dispatch units and improved Command Streamers designed to evaluate dynamic execution queues directly.
  • Upgraded Cache Architecture: By expanding the L1 and L2 cache pipelines and supporting low-overhead scratchpad allocation, Xe2 provides native silicon backing for the dynamic expansion of Work Graph nodes.

Summary

True native acceleration for DirectX 12 Work Graphs—free from CPU involvement or driver-emulated scheduling compute loops—is currently realized across:

  1. AMD RDNA 3 and RDNA 3.5 (Radeon RX 7000 series, Radeon 700M/800M series).
  2. NVIDIA Ada Lovelace (GeForce RTX 40 series, RTX workstation Ada generation) and Ampere (RTX 30 series).
  3. Intel Xe2 (Battlemage and Core Ultra 200V series).

These architectures allow the GPU to function as a self-sufficient processor, handling pipeline generation, memory allocation, and dispatch logic entirely within local silicon.