DirectX 12 Render Pass Optimizations for TBDR GPUs

The DirectX 12 Render Pass API optimizes rendering performance by giving developers fine-grained control over how render targets are bound, accessed, and resolved during a defined scope of draw calls. For mobile and tile-based deferred rendering (TBDR) architectures, these declarations act as vital driver and hardware hints. By explicitly communicating how data flows into and out of render targets, the API allows GPUs to maximize on-chip tile cache utilization and drastically reduce memory bandwidth round-trips to power-hungry external DRAM.

The Tile-Based Rendering Bottleneck

Traditional immediate-mode desktop GPUs render geometry directly to full-frame allocations in high-bandwidth VRAM. In contrast, mobile and tile-based GPUs divide the screen into small regions, typically 16x16 or 32x32 pixel tiles.

Each tile is loaded into small, fast, on-chip tile memory (SRAM), where all rasterization, depth testing, and pixel shading occur. Once processing for a tile finishes, the completed data is written back to main system memory (LPDDR/DRAM). The most expensive operation on these architectures is not computation, but transferring data across the system bus. Without explicit workload boundaries, the GPU driver must conservatively assume that render targets contain data needed from prior frames and that all outputs must be written back to DRAM, causing severe bandwidth and thermal bottlenecks.

Explicit Load and Store Actions

The DirectX 12 Render Pass API addresses this through beginning and ending access flags (D3D12_RENDER_PASS_BEGINNING_ACCESS and D3D12_RENDER_PASS_ENDING_ACCESS). These access types define precisely what the hardware must do with on-chip tile memory when a render pass starts and concludes:

  • Beginning Access (Load Optimization):
    • CLEAR: Instructs the GPU to zero-initialize or set the tile buffer to a clear color within on-chip memory directly, eliminating the need to read old texture data from DRAM.
    • DISCARD: Notifies the GPU that the current buffer contents are unneeded and will be overwritten, allowing the hardware to skip loading data into the tile cache entirely.
    • PRESERVE: Forces the GPU to fetch existing pixels from DRAM into on-chip cache only when previous contents are genuinely required for blending or incremental drawing.
  • Ending Access (Store Optimization):
    • STORE / PRESERVE: Explicitly flushes the finished tile cache data to DRAM.
    • DISCARD: Tells the hardware that the contents (such as intermediate depth buffers or transient stencil passes) are no longer needed. The GPU simply discards the tile cache contents without spending memory bandwidth writing them back to main memory.
    • RESOLVE: Allows the hardware to resolve multisample anti-aliasing (MSAA) directly within the on-chip tile memory before writing a single resolved image back to DRAM, bypassing the need to store massive multi-sample buffers in system memory.

Transient Resources and Subpass Layouts

Complex rendering pipelines, such as deferred shading, rely heavily on intermediate G-buffers (normal, albedo, roughness, and depth). On traditional APIs, each G-buffer target is written to DRAM and then immediately read back in a subsequent lighting pass.

With the Render Pass API, developers can designate these intermediate targets as transient. A TBDR GPU can retain the G-buffer data entirely within its local tile cache across consecutive subpasses. The geometry pass populates the on-chip G-buffer, and the lighting pass immediately consumes it within the same tile memory before the pass ends. The intermediate data is then discarded, ensuring that high-density G-buffer data never leaves the chip or consumes external memory bandwidth.

Cache Coherency and Reduced State Flushes

Before the introduction of render passes, DirectX 12 relied entirely on ResourceBarrier calls to synchronize pipeline stages and transition resource states. While effective, fine-grained barriers can force a tile-based GPU to flush its local tile caches prematurely to guarantee cache coherency across different draw operations.

The Render Pass API groups these operations into a unified execution block. Knowing the start, operations, and end of a pass allows the hardware scheduler to:

  1. Defer Cache Invalidation: The hardware avoids flushing L1/L2 caches between individual draw calls within the pass.
  2. Optimize Layout Transitions: State transitions for render targets and depth-stencil surfaces can be deferred until the entire tile workload is complete.
  3. Batch Geometry Processing: The GPU can bin all tile primitives efficiently, knowing that render target states remain static for the duration of the pass.

By removing the guesswork from render target management, the DirectX 12 Render Pass API transforms high-level pipeline intent into actionable layout and cache hints, directly aligning modern graphics engines with the hardware constraints of mobile and tile-based architectures.