How #pragma pack Alters C++ Structure Alignment

This article examines the #pragma pack directive in C++, exploring how it overrides the compiler's default memory alignment rules for user-defined data structures. By dictating the maximum byte alignment of structure members, #pragma pack reduces or completely eliminates padding bytes between fields. The following sections detail default compiler alignment behavior, the exact mechanics of how packing modifies memory layouts, the common push-and-pop syntax, and the critical trade-offs between reduced memory usage and CPU execution performance.

Default Structure Alignment in C++

By default, modern C++ compilers align data types in memory based on their natural boundaries to optimize hardware access. For instance, a 1-byte char can be stored at any memory address, a 2-byte short typically aligns on an even address, an 8-byte double aligns on an address divisible by 8, and a 4-byte int aligns on an address divisible by 4.

When creating a structure containing mixed data types, the compiler inserts unused memory—known as padding—between fields and at the end of the structure. This ensures that every member begins at an address suited to its type and that arrays of the structure maintain that alignment across all elements.

Consider this standard layout:

struct Example {
    char a;     // 1 byte
    // 3 bytes of padding inserted here
    int b;      // 4 bytes
    char c;     // 1 byte
    // 3 bytes of padding added to round to 4-byte alignment
};

Although the useful data totals 6 bytes, sizeof(Example) evaluates to 12 bytes due to 6 bytes of compiler-inserted padding.

How #pragma pack Modifies Alignment

The #pragma pack(n) directive alters this behavior by establishing an upper bound, \(n\), for the alignment of structure members, where \(n\) is commonly a power of two (such as 1, 2, 4, 8, or 16).

When #pragma pack(n) is active, the compiler calculates the alignment boundary for each member using the following rule:

\[\text{Member Alignment} = \min(\text{sizeof(member)}, n)\]

  • If \(n = 1\), all padding is disabled entirely because every type aligns to a multiple of 1.
  • If \(n = 2\), members larger than 2 bytes (such as 4-byte integers or 8-byte pointers) align to 2-byte boundaries instead of their natural 4- or 8-byte boundaries.
  • If \(n\) is greater than or equal to a member's natural alignment, that member retains its natural alignment.

The total size of the structure is also rounded up to a multiple of \(\min(\text{largest member alignment}, n)\) rather than the largest member's full natural alignment.

Mechanics in Action

Applying #pragma pack(1) to the previous structure forces full packing:

#pragma pack(push, 1)
struct PackedExample {
    char a;     // Offset 0, size 1 byte
    int b;      // Offset 1, size 4 bytes (no padding before)
    char c;     // Offset 5, size 1 byte
};
#pragma pack(pop)

With packing set to 1 byte:

  1. a occupies offset 0.
  2. b starts immediately at offset 1, even though it is a 4-byte integer.
  3. c starts immediately at offset 5.
  4. No tail padding is appended.

Consequently, sizeof(PackedExample) drops from 12 bytes to exactly 6 bytes.

Managing Scope with Push and Pop

Because #pragma pack affects all structures declared after its invocation, leaving it open can unintentionally disrupt other data structures, third-party libraries, or standard library headers. To localize changes, compilers support an internal alignment stack using push and pop:

  • #pragma pack(push, n) saves the current alignment state onto the compiler's internal stack and sets the new alignment to \(n\).
  • #pragma pack(pop) restores the alignment state that existed prior to the corresponding push.

This mechanism guarantees that custom packing rules apply exclusively to the intended structures.

Performance and Hardware Trade-Offs

While #pragma pack is valuable for mapping data directly to network packets, binary file formats, and hardware registers, it introduces hardware-level consequences:

  • Unaligned Memory Access: When a multi-byte value spans across cache lines or word boundaries, modern CPUs require multiple memory cycles and bitwise assembly operations to read or write the data, decreasing instruction throughput.
  • Hardware Faults: Some architectures (such as specific ARM or SPARC processors) do not support unaligned memory access in hardware. On these platforms, accessing an unaligned member directly can trigger an alignment fault or kernel trap, severely degrading performance or crashing the process.
  • Cache Efficiency vs. CPU Overhead: While packed structures fit more instances into the CPU cache, the overhead of reading unaligned data frequently offsets any spatial locality benefits in computationally intensive tasks.