Why Is Threshold Voltage Scaling Hard for Dynamic Power?

Threshold voltage scaling presents a major challenge in classical computing because lowering the threshold voltage to reduce dynamic power consumption causes an exponential increase in static leakage current. While reducing the supply voltage is one of the most effective ways to cut active power, doing so without also lowering the threshold voltage degrades switching speed and overall performance. This creates a fundamental trade-off between dynamic power, static power, and circuit speed that limits how far classical transistors can be scaled.

The Relationship Between Supply Voltage and Dynamic Power

In classical CMOS circuits, dynamic power is the energy consumed when transistors switch states to charge and discharge load capacitances. It is governed by the equation:

\[P_{dyn} = \alpha C V_{dd}^2 f\]

In this formula, \(\alpha\) is the activity factor, \(C\) is the total load capacitance, \(V_{dd}\) is the supply voltage, and \(f\) is the clock frequency. Because dynamic power scales with the square of the supply voltage (\(V_{dd}^2\)), reducing \(V_{dd}\) is the most direct way to lower active power consumption.

Why Threshold Voltage Must Scale Too

Lowering \(V_{dd}\) alone introduces a performance penalty. The switching speed of a transistor depends on the overdrive voltage, which is the difference between the supply voltage and the threshold voltage (\(V_{dd} - V_{th}\)). When \(V_{dd}\) is reduced while \(V_{th}\) remains fixed, the gate overdrive shrinks, reducing the drive current and slowing down the circuit.

To maintain high switching speeds and clock frequencies at a lower \(V_{dd}\), engineers must scale down \(V_{th}\) proportionally.

The Subthreshold Leakage Problem

Reducing \(V_{th}\) comes with a severe side effect: subthreshold leakage current. Even when a transistor is nominally turned off, a small amount of current continues to flow between the source and drain. This leakage current (\(I_{leak}\)) increases exponentially as \(V_{th}\) decreases:

\[I_{leak} \propto e^{-\frac{V_{th}}{n V_T}}\]

Here, \(n\) is the subthreshold slope factor and \(V_T\) is the thermal voltage. Because of this exponential relationship, even a modest reduction in \(V_{th}\) can cause static power consumption (\(P_{stat} = V_{dd} \cdot I_{leak}\)) to skyrocket, especially in modern processors with billions of transistors.

The Fundamental Trade-Off

This interplay creates a bottleneck known as the power-performance wall. If \(V_{dd}\) and \(V_{th}\) are lowered together to save dynamic power without losing speed, static leakage power dominates the total power budget, wasting energy even when the chip is idle. Conversely, if \(V_{th}\) is kept high to suppress leakage, \(V_{dd}\) cannot be lowered significantly without sacrificing performance.

As a result, classical computing has largely hit a floor on how low \(V_{dd}\) and \(V_{th}\) can be pushed, forcing chip designers to rely on architectural techniques such as multi-core processing, power gating, and specialized accelerators to continue improving energy efficiency.