Why is EUV lithography needed for sub-7nm chips?

Extreme ultraviolet lithography is necessary for printing sub-7-nanometer circuit features because conventional deep ultraviolet light has too long a wavelength to resolve tiny transistor patterns cleanly. By switching from 193-nanometer light to 13.5-nanometer extreme ultraviolet light, chipmakers can print much smaller features in a single exposure, avoid the compounding errors and costs of complex multi-patterning, and keep classical computing chips scaling in density and efficiency.

The Physics Limit of Optical Lithography

In photolithography, a light source projects a circuit pattern through a photomask and a system of lenses onto a silicon wafer coated with light-sensitive photoresist. The minimum feature size, or critical dimension (\(CD\)), that an optical system can print is governed by the Rayleigh criterion:

\[CD = k_1 \frac{\lambda}{NA}\]

In this equation, \(\lambda\) is the wavelength of the light source, \(NA\) is the numerical aperture of the projection optics, and \(k_1\) is a process-dependent factor that reflects how aggressively engineers optimize the illumination, mask, and resist. Under classical diffraction limits, \(k_1\) cannot be pushed below \(0.25\) for a single exposure.

For decades, the semiconductor industry relied on deep ultraviolet (DUV) lithography using argon fluoride (ArF) lasers at \(\lambda = 193\text{ nm}\). Even with immersion lithography, where purified water fills the gap between the final lens and the wafer to raise the effective \(NA\) to \(1.35\), the physical resolution limit of a single 193-nanometer exposure sits around \(36\text{ nm}\) to \(38\text{ nm}\) half-pitch. That is far too coarse for sub-7-nanometer nodes, where metal pitches and gate lengths shrink into the teens and single digits of nanometers.

Why Multi-Patterning Hits a Wall

Before extreme ultraviolet (EUV) lithography became production-ready, chipmakers stretched 193-nanometer immersion DUV beyond its single-exposure limit using multi-patterning techniques. Methods such as Litho-Etch-Litho-Etch (LELE) and Self-Aligned Quadruple Patterning (SAQP) split a dense circuit layer into multiple sparser masks, printing and etching them sequentially to achieve tighter spacing.

While multi-patterning enabled early 10-nanometer and 7-nanometer processes, it introduces severe drawbacks at smaller geometries:

  • Overlay errors: Each additional exposure must align with previous layers to within a couple of nanometers. Misalignment causes shorts, open circuits, or degraded transistor performance.
  • Exploding cycle times and cost: Replacing one lithography step with three or four exposures, plus extra deposition and etch steps, dramatically increases wafer fabrication time, mask count, and defect opportunities.
  • Design restrictions: Self-aligned spacer techniques work well for regular, repeating lines, but they restrict two-dimensional routing flexibility needed for complex logic cells.

How 13.5-Nanometer Light Solves the Problem

EUV lithography tackles the Rayleigh equation directly by slashing \(\lambda\) from \(193\text{ nm}\) down to \(13.5\text{ nm}\)—more than a 14-fold reduction. Even though current EUV systems use a lower numerical aperture (\(NA = 0.33\), with High-NA systems at \(NA = 0.55\) entering use), the massive drop in wavelength easily outweighs the smaller \(NA\), allowing single-exposure printing of features that previously required quadruple patterning with DUV.

Printing with \(13.5\text{ nm}\) light requires a completely different optical architecture. Because almost all materials—including air and glass lenses—absorb EUV light, the entire exposure path must operate in a vacuum using specialized reflective mirrors coated with alternating layers of molybdenum and silicon.

Impact on Classical Computing Scaling

For classical computing processors—CPUs, GPUs, and AI accelerators—moving to sub-7-nanometer nodes is essential for packing more transistors per square millimeter while controlling power consumption. EUV lithography restores single-exposure patterning for critical metal and via layers, which tightens feature-to-feature placement, reduces variability, and improves manufacturing yield. Without EUV, continuing transistor scaling below 7 nanometers would be economically and physically impractical.