Why Do Transparent D Latches Cause Race Conditions?

Level-sensitive transparent D latches are susceptible to race conditions because their outputs continuously track their data inputs for the entire duration that the clock or enable signal is active. In synchronous digital circuits, this transparency window allows signals to propagate through multiple combinational logic stages and latches within a single clock phase, leading to timing violations and unpredictable state changes. Edge-triggered flip-flops avoid this problem by sampling the input only at a discrete clock transition, isolating sequential stages from one another.

How Level-Sensitive Transparency Works

A D latch has a data input \(D\), an enable or clock input \(E\), and an output \(Q\). When \(E\) is at its active level (typically high, \(E = 1\)), the latch is transparent:

\[Q(t) = D(t)\]

Any change on \(D\) passes directly to \(Q\) after a short propagation delay \(t_{pd}\). When \(E\) returns to its inactive level (\(E = 0\)), the latch holds the last value present on \(D\) before the transition.

The Mechanism of Race-Through

Race conditions occur when the output of one latch feeds into the input of another latch through combinational logic, and both latches share the same active clock phase. Because both latches are transparent at the same time, a signal can "race through" the first latch, traverse the combinational logic, and reach the second latch before the clock pulse ends.

For a race-through fault to occur, the total delay from the first latch's output to the second latch's input must be shorter than the active pulse width of the clock \(t_{pw}\):

\[t_{pd,latch} + t_{comb} < t_{pw}\]

When this inequality holds, the second latch captures the new data from the current clock cycle instead of the intended data from the previous cycle. This corrupts the pipeline state and makes the circuit sensitive to variations in gate delays, temperature, and supply voltage.

Why Edge-Triggered Flip-Flops Prevent Races

An edge-triggered D flip-flop samples \(D\) only on a specific clock edge (rising or falling) and updates \(Q\) shortly afterward. Outside of a narrow setup and hold window around that clock edge, changes on \(D\) have no effect on \(Q\).

In a chain of edge-triggered flip-flops sharing the same clock, the new value at the output of the first flip-flop appears after the clock-to-Q delay \(t_{cq}\). By the time this new value propagates through the combinational logic, the active clock edge has already passed, and the second flip-flop will not sample it until the next clock cycle. The timing requirement shifts from a pulse-width constraint to a minimum-delay hold constraint:

\[t_{cq} + t_{comb} > t_{hold}\]

Because \(t_{cq}\) is typically larger than \(t_{hold}\), edge-triggered designs are far more robust against race conditions than single-phase level-sensitive latch designs.

Mitigating Races in Latch-Based Designs

When designers use latches for area or power savings, they typically avoid race conditions by using two-phase non-overlapping clocks (\(\phi_1\) and \(\phi_2\)). In this scheme, adjacent latches are driven by alternating clock phases that are never active simultaneously, ensuring that no two consecutive latches are transparent at the same time.