Why Are Carbon Nanotube Transistors Studied Over Silicon?

Carbon nanotube field-effect transistors are investigated as replacements for silicon channels in classical computing because single-walled carbon nanotubes offer exceptional carrier mobility, superior electrostatic control at nanometer scales, and near-ballistic charge transport. As conventional silicon transistors approach physical scaling limits, these properties allow faster switching and lower power consumption without severe short-channel degradation.

Superior Carrier Mobility and Ballistic Transport

In classical complementary metal-oxide-semiconductor (CMOS) logic, transistor switching speed depends heavily on how quickly charge carriers move through the channel. Single-walled carbon nanotubes (SWCNTs) exhibit intrinsic carrier mobilities that can exceed those of bulk silicon by an order of magnitude.

Because of their one-dimensional structure and strong covalent carbon-carbon bonds, electrons and holes in SWCNTs experience minimal backscattering from phonons. At channel lengths below \(10\text{ nm}\), carriers can travel nearly ballistically from source to drain, meaning the drive current \(I_{\text{on}}\) remains high even as the device shrinks.

Electrostatic Control at Nanometer Scales

As silicon channels are scaled down, the gate loses electrostatic control over the channel, leading to short-channel effects such as drain-induced barrier lowering (DIBL) and increased off-state leakage current. Thinning silicon down to a few nanometers to restore gate control causes severe surface roughness scattering, which degrades carrier mobility.

Carbon nanotubes naturally have an atomically thin body with diameters typically between \(1\text{ nm}\) and \(2\text{ nm}\) and no dangling bonds on their surface. This geometry allows the gate to wrap around or couple tightly to the channel, maintaining steep subthreshold swings close to the theoretical thermal limit of approximately \(60\text{ mV/decade}\) at room temperature (\(300\text{ K}\)).

Lower Power Consumption and Energy-Delay Product

Dynamic power dissipation in digital circuits scales quadratically with supply voltage \(V_{DD}\):

\[P_{\text{dyn}} = \alpha C V_{DD}^2 f\]

Because carbon nanotube field-effect transistors achieve high drive currents at reduced \(V_{DD}\), they can operate at lower voltages while maintaining or exceeding the clock frequencies \(f\) of silicon devices. This combination reduces both dynamic power and the overall energy-delay product, which is critical for dense, high-performance processors.

Symmetric Electron and Hole Transport

In silicon, electron mobility is roughly two to three times higher than hole mobility, requiring p-type transistors to be sized wider than n-type transistors to balance rise and fall times. In semiconducting SWCNTs, the conduction and valence bands are nearly symmetric around the Fermi level, giving electrons and holes similar effective masses and mobilities. This symmetry simplifies circuit layout and reduces area overhead in CMOS logic gates.

Remaining Integration Challenges

Despite their channel advantages, carbon nanotube transistors face manufacturing hurdles before they can replace silicon at scale. Achieving high-purity semiconducting nanotube populations without metallic impurities, aligning nanotubes at high density with uniform pitch, and minimizing metal-to-nanotube contact resistance remain active areas of semiconductor research.