Where Does a CPU Fetch Its First Instruction on Reset?
When a classical computer receives a power-good signal and releases the processor from reset, the CPU does not start by reading from RAM or a hard drive. Instead, its internal hardware forces the instruction pointer to a predetermined memory address known as the reset vector. This address points to non-volatile firmware stored in read-only memory or flash memory, which contains the very first instructions needed to initialize the system.
The Role of the Reset Vector
Before any operating system or software can run, a processor needs a reliable starting point. Because system RAM is empty and uninitialized when power is first applied, the CPU cannot fetch instructions from it. To solve this, processor designers hardwire a specific starting address—the reset vector—into the CPU's silicon.
Upon receiving a power-good signal, the CPU's control unit clears its internal registers, sets the instruction pointer (or program counter) to the reset vector, and issues its first memory read request. The system chipset or memory controller intercepts this specific address range and routes it to the motherboard's non-volatile firmware chip, typically a Serial Peripheral Interface (SPI) flash chip holding the BIOS or UEFI.
How Different Architectures Handle Reset
While the concept of a reset vector is universal in classical computing, the exact address and mechanism vary by processor architecture:
- x86 and x86-64: On modern Intel and AMD processors,
the CPU starts in a legacy 16-bit compatibility mode called real mode.
The instruction pointer (
EIP) is set to0x0000FFF0, and the code segment (CS) base is set to0xFFFF0000, resulting in a physical starting address of0xFFFFFFF0—just 16 bytes below the 4 GB boundary. Because 16 bytes is too small for a full firmware program, the instruction at0xFFFFFFF0is almost always aJMP(jump) instruction that redirects execution to the main BIOS or UEFI initialization code. - ARM (Cortex-M): Microcontroller-class ARM cores use
a vector table located at address
0x00000000by default. Rather than executing an instruction directly at that address, the CPU reads the initial stack pointer value from0x00000000and the address of the reset handler from0x00000004, then branches to that handler. - ARM (Cortex-A / ARMv8-A): Application-class ARM
processors typically start execution at a hardware-defined reset address
(often
0x00000000or a configurable base address via theRVBAR_EL3register) in the highest privilege level, jumping directly into the first-stage bootloader stored in on-chip Boot ROM. - RISC-V: The RISC-V specification leaves the exact reset vector address implementation-defined, allowing chip designers to point it to an internal Boot ROM or external flash memory.
From Firmware to Operating System
The first instructions fetched from the reset vector are responsible for basic hardwarebring-up. The firmware configures the CPU caches, initializes the memory controller so that DRAM becomes usable, and performs a Power-On Self-Test (POST). Once RAM is ready, the firmware copies itself or a bootloader into memory and hands off control, eventually loading the operating system kernel.