What Is Memory-Mapped vs Port-Mapped I/O?

In classical computing, processors communicate with peripheral devices using two primary addressing architectures: memory-mapped I/O and isolated port-mapped I/O. Memory-mapped I/O places device registers into the same address space as main system memory, allowing standard memory instructions to access hardware. Isolated port-mapped I/O maintains a separate address space dedicated exclusively to peripherals, requiring specialized processor instructions and dedicated control signals.

Address Space Organization

The fundamental architectural distinction lies in how the CPU organizes its addressable locations.

In memory-mapped I/O (MMIO), both RAM and peripheral control registers share a single unified address space. If a system has a 32-bit address bus, it can address \(2^{32}\) bytes total, and a portion of that range is reserved for hardware devices rather than physical memory. Address decoding logic on the motherboard or system bus routes read and write requests to either RAM or the appropriate device depending on the target address.

In isolated port-mapped I/O (PMIO), also known as isolated I/O, the CPU maintains two distinct address spaces: one for memory and one for I/O ports. A device register at port address 0x60 does not conflict with memory address 0x60 because they are accessed through different mechanisms.

Instruction Set and Hardware Signals

Because the address spaces differ, the CPU uses different instructions and bus signals to interact with them.

With MMIO, the processor uses its standard memory-access instructions, such as MOV, LOAD, or STORE. Any instruction that can read from or write to RAM can also manipulate a peripheral register. This means the full power of the CPU's addressing modes and arithmetic operations is available for device control, and no extra opcodes are needed in the instruction set architecture.

With PMIO, the CPU must provide dedicated I/O instructions, such as IN and OUT on x86 architectures. When executing these instructions, the processor asserts a specific control pin—such as an \(M/\overline{IO}\) (Memory / Input-Output) signal—to inform the bus and chipset whether the current address on the bus refers to main memory or an I/O port.

Trade-offs and Modern Usage

Each approach carries distinct advantages and constraints:

  • Address Space Consumption: MMIO reduces the total amount of physical RAM a system can directly address, since device registers occupy part of the memory map. PMIO preserves the entire memory address space for RAM.
  • Instruction Complexity: MMIO keeps the instruction set simpler and more uniform, which is why RISC architectures like ARM and RISC-V rely almost exclusively on it. PMIO requires additional opcodes and control logic.
  • Security and Caching: MMIO benefits from standard virtual memory and page-table protection mechanisms, though device regions must be marked as uncacheable so the CPU does not read stale hardware state. PMIO separates device access at the hardware level, using dedicated privilege checks for I/O instructions.

Modern x86 systems support both architectures, retaining legacy PMIO ports for backward compatibility while using MMIO for high-speed devices like graphics cards and NVMe drives. Most other modern architectures use MMIO exclusively.