What Caused the Breakdown of Dennard Scaling Around 2005?

Dennard scaling broke down around 2005 because transistors became so small that electrical current began leaking through them even when they were turned off, preventing engineers from lowering operating voltages any further. Without lower voltage to offset the heat generated by faster switching, increasing clock speeds caused chips to overheat, forcing the computing industry to abandon single-core frequency scaling in favor of multi-core architectures.

How Dennard Scaling Originally Worked

Formulated by Robert H. Dennard and his colleagues in 1974, Dennard scaling observed that as transistors shrank, their power density remained roughly constant. When transistor dimensions were scaled down by a factor of \(\kappa\) (where \(\kappa > 1\)), the capacitance \(C\) and operating voltage \(V\) could both be reduced by \(\kappa\), while the switching frequency \(f\) could increase by \(\kappa\).

Dynamic power consumption in a CMOS circuit is governed by the equation:

\[P_{\text{dynamic}} = \alpha C V^2 f\]

where \(\alpha\) is the activity factor. Because \(C\) decreased by \(\kappa\), \(V^2\) decreased by \(\kappa^2\), and \(f\) increased by \(\kappa\), the total power per transistor fell by \(\kappa^2\). Since the number of transistors per unit area increased by \(\kappa^2\), the overall power density of the chip stayed constant. This allowed CPU clock frequencies to climb from megahertz to several gigahertz without melting the silicon.

The Rise of Leakage Current

By the mid-2000s, transistor gate lengths had shrunk below 100 nanometers, and the insulating gate oxide layer had thinned to just a few atoms thick. At this scale, quantum mechanical effects and short-channel effects caused significant static power dissipation, known as leakage current.

Two primary mechanisms drove this leakage:

• Subthreshold leakage: To keep transistors switching quickly at lower supply voltages \(V_{dd}\), engineers also had to lower the threshold voltage \(V_{th}\) required to turn a transistor on. However, lowering \(V_{th}\) exponentially increased the current leaking between the source and drain even when the transistor was in the "off" state.
• Gate oxide tunneling: As the silicon dioxide insulator became only a few atomic layers thick, electrons began tunneling directly through the barrier, creating continuous current draw.

Because static power (\(P_{\text{static}} = V_{dd} \cdot I_{\text{leak}}\)) grew rapidly, further reductions in \(V_{dd}\) and \(V_{th}\) became impossible without making the chip waste unacceptable amounts of energy as heat while idle.

The Thermal Wall and the Shift to Multi-Core

Once supply voltage hit a practical floor around \(1\text{ V}\), the \(V^2\) term in the dynamic power equation could no longer offset increases in capacitance and frequency. Pushing clock frequencies higher caused power density to spike sharply, hitting a thermal limit often called the "power wall." Air cooling could no longer dissipate the heat generated by a single, faster core.

Unable to rely on higher clock speeds for performance gains, CPU manufacturers pivoted around 2005 to multi-core processors. Instead of making one core run faster, engineers used the growing transistor budget from Moore's Law to place multiple, slower cores on a single die, shifting the burden of performance scaling to parallel computing.