How Does the MESI Cache Coherency Protocol Work?

The MESI cache coherency protocol is a widely used invalidation-based protocol that keeps data consistent across private caches in multicore classical processors. By assigning one of four states—Modified, Exclusive, Shared, or Invalid—to every cache line, it ensures that all cores observe a coherent view of shared memory without unnecessary bus traffic. This article explains what each state represents, how cores transition between states during reads and writes, and how bus snooping coordinates these transitions.

Why Multicore Systems Need Cache Coherency

In a multicore processor, each core typically has its own private L1 and L2 caches to reduce memory latency. When multiple cores read and write to the same memory address, copies of that data can exist in several caches simultaneously. Without a coherency mechanism, one core could modify its local copy while another core continues reading stale data from its own cache.

The MESI protocol solves this problem using a write-invalidate approach. Before a core can write to a cache line, it must ensure that all other cached copies of that line are invalidated.

The Four MESI States

Every cache line in a core's private cache is tagged with two bits that encode one of four states:

  • Modified (M): The cache line is present only in the current core's cache, and it has been modified relative to main memory (it is "dirty"). The core has exclusive permission to read and write this line, and it is responsible for writing the updated data back to main memory before any other core can read it.
  • Exclusive (E): The cache line is present only in the current core's cache, and it matches main memory (it is "clean"). The core can read the line or silently transition it to the Modified state on a write without notifying other cores.
  • Shared (S): The cache line may be present in multiple cores' caches, and all copies match main memory. Cores can read the line freely, but no core can write to it without first broadcasting an invalidation signal.
  • Invalid (I): The cache line does not contain valid data. Any read or write to an Invalid line results in a cache miss, requiring the core to fetch the data from another cache or main memory.

State Transitions and Bus Snooping

Cores coordinate state changes by monitoring a shared interconnect or bus, a technique known as bus snooping. Each cache controller watches for memory requests issued by other cores and updates its own cache line states accordingly.

Read Operations

When a core attempts to read a memory address:

  1. Cache Hit (M, E, or S): The core reads the data directly from its local cache with no bus activity.
  2. Cache Miss (I): The core broadcasts a read request on the bus.
    • If no other core holds the line, main memory supplies the data, and the requesting core places the line in the Exclusive state.
    • If another core holds the line in the Exclusive or Shared state, that core signals its presence, and the requesting core places the line in the Shared state. The original holder (if in Exclusive) also transitions its copy to Shared.
    • If another core holds the line in the Modified state, that core intercepts the request, writes the dirty data back to main memory (or forwards it directly), and transitions its own copy to Shared. The requesting core then loads the line in the Shared state.

Write Operations

When a core attempts to write to a memory address:

  1. Hit in Modified (M): The core updates its local cache line immediately with no bus traffic.
  2. Hit in Exclusive (E): The core updates its local cache line and silently transitions the state from Exclusive to Modified. Because no other core holds a copy, no bus broadcast is needed.
  3. Hit in Shared (S): The core broadcasts a "Read For Ownership" (RFO) or invalidation message on the bus. All other cores holding the line transition their copies to Invalid. Once acknowledged, the writing core updates its copy and transitions to Modified.
  4. Miss (I): The core broadcasts an RFO request on the bus to fetch the latest data and invalidate all other copies. If another core holds the line in Modified, it flushes the dirty data first. The requesting core then loads the line, applies its write, and sets the state to Modified.

Performance Benefits and Limitations

The Exclusive state is what distinguishes MESI from simpler protocols like MSI. When a single thread reads and then modifies a variable—a very common pattern—the line starts in Exclusive and transitions to Modified without generating a bus invalidation. This reduces interconnect traffic and improves scalability.

However, MESI can still suffer from false sharing, where two cores modify different variables that happen to reside on the same cache line, causing the line to ping-pong between caches. Additionally, when a core reads a Modified line from another core, MESI often requires writing the dirty line back to main memory. Extensions such as MOESI add an Owned state to allow direct cache-to-cache transfers of dirty data without immediate memory write-backs.