How Does Subthreshold Leakage Cause Static Power?

Subthreshold leakage current is a major source of static power dissipation in nanometer-scale classical computing chips. As transistor dimensions shrink below tens of nanometers, transistors no longer turn off completely when their gate voltage is below the threshold voltage. This residual current flows continuously between the drain and source terminals even when a logic gate is idle, steadily consuming energy and generating heat across billions of transistors.

What Is Subthreshold Leakage Current?

In an ideal metal-oxide-semiconductor field-effect transistor (MOSFET), no current flows when the gate-to-source voltage \(V_{GS}\) is below the threshold voltage \(V_{th}\). In real nanometer-scale devices, however, charge carriers still diffuse from the source to the drain due to thermal energy. This weak-inversion conduction is known as subthreshold leakage current.

The subthreshold current \(I_{sub}\) depends exponentially on the difference between the gate-to-source voltage and the threshold voltage:

\[I_{sub} \propto \exp\left(\frac{V_{GS} - V_{th}}{n V_T}\right)\]

Here, \(n\) is the subthreshold slope factor (typically between \(1.2\) and \(1.5\) for bulk silicon MOSFETs), and \(V_T = \frac{kT}{q}\) is the thermal voltage, which is approximately \(26\text{ mV}\) at room temperature (\(300\text{ K}\)).

Why Nanometer Scaling Makes Leakage Worse

As semiconductor fabrication nodes scale down, supply voltage \(V_{DD}\) must also be reduced to keep dynamic power and electric fields within safe limits. To maintain fast switching speeds at a lower \(V_{DD}\), chip designers must lower the threshold voltage \(V_{th}\) as well.

Because \(I_{sub}\) increases exponentially as \(V_{th}\) decreases, even a modest reduction in threshold voltage causes a dramatic rise in off-state leakage. Additionally, short-channel effects in nanometer transistors—such as drain-induced barrier lowering (DIBL)—further reduce the effective energy barrier between source and drain, allowing more current to leak when the transistor is supposed to be off.

From Leakage Current to Static Power Dissipation

Static power dissipation is the power consumed by a circuit when it is powered on but not actively switching. For a single idle transistor or logic gate, the static power \(P_{static}\) due to subthreshold leakage is given by:

\[P_{static} = V_{DD} \cdot I_{sub}\]

While the leakage current of one transistor is tiny (often measured in nanoamperes), modern processors contain tens of billions of transistors. At any given moment, a large fraction of these transistors are in an idle state. Summing \(V_{DD} \cdot I_{sub}\) across the entire chip results in substantial continuous power draw, which can rival or even exceed dynamic switching power in deeply scaled technologies.

Thermal Runaway and Temperature Effects

Subthreshold leakage is also strongly sensitive to temperature. As a chip heats up due to dynamic and static power dissipation, the thermal voltage \(V_T\) increases and the threshold voltage \(V_{th}\) decreases. Both effects cause \(I_{sub}\) to rise exponentially, which in turn generates more heat. If cooling is insufficient, this positive feedback loop can lead to thermal runaway, degrading performance and reliability.

Mitigation Techniques in Modern Chips

Chip architects use several circuit and device-level strategies to curb subthreshold leakage in nanometer-scale processors:

  • Multi-threshold CMOS (MTCMOS): Critical timing paths use low-\(V_{th}\) transistors for speed, while non-critical paths use high-\(V_{th}\) transistors to minimize leakage.
  • Power gating: Sleep transistors disconnect idle functional blocks from the power supply, eliminating static power in unused regions.
  • Advanced transistor geometries: FinFETs and gate-all-around (GAA) nanosheet transistors wrap the gate around the channel on multiple sides, improving electrostatic control and steepening the subthreshold slope.
  • Body biasing: Applying a reverse bias to the transistor body increases \(V_{th}\) during idle periods to suppress leakage.