How Does DDR SDRAM Transfer Data on Both Clock Edges?

Double Data Rate synchronous dynamic random-access memory (DDR SDRAM) doubles data transfer rates compared to single data rate memory by transmitting data on both the rising and falling edges of the clock signal. Rather than speeding up the internal memory array itself, DDR SDRAM relies on a prefetch architecture, differential clocking, a dedicated data strobe signal, and a delay-locked loop to synchronize high-speed transfers between the memory chip and the memory controller.

From Single Data Rate to Double Data Rate

In classical synchronous DRAM (SDR SDRAM), data is sampled only once per clock cycle, typically on the rising edge of the system clock. If the clock frequency is \(f\), the data transfer rate per pin is \(f\) transfers per second.

DDR SDRAM keeps the same clock frequency \(f\) for commands and addresses, but transfers data on both the rising and falling edges of the clock. This yields a data rate of \(2f\) transfers per second per pin, often expressed in megatransfers per second (\(\text{MT/s}\)).

The Prefetch Architecture

The internal DRAM cell array cannot easily switch twice as fast as the external bus. To bridge this gap, DDR SDRAM uses a prefetch buffer that reads or writes multiple bits in parallel from the internal array during each internal clock cycle, then serializes them onto the external data pins (\(DQ\)) at twice the clock rate.

In the original DDR specification, a \(2n\) prefetch architecture is used:

  1. During a read operation, the memory array fetches \(2\) bits of data per \(DQ\) pin in a single internal clock cycle.
  2. Those \(2\) bits are loaded into a multiplexer.
  3. The multiplexer outputs the first bit on the rising edge of the clock and the second bit on the falling edge.

Later generations increased the prefetch depth—\(4n\) for DDR2, \(8n\) for DDR3 and DDR4, and \(16n\) for DDR5—allowing the external I/O bus to run much faster than the internal memory core.

Differential Clocking and Timing Precision

At high frequencies, single-ended clock signals suffer from noise and duty-cycle distortion, where the rising and falling edges are not spaced exactly \(180^\circ\) apart. DDR SDRAM solves this by using a differential clock pair, \(CK\) and \(\overline{CK}\) (often written \(CK\#\)).

The memory device determines the exact timing of the rising edge where \(CK\) crosses above \(\overline{CK}\), and the falling edge where \(CK\) crosses below \(\overline{CK}\). Using the crossing point of two complementary signals reduces sensitivity to common-mode noise and ensures that both edges are accurately defined.

The Role of the Data Strobe (\(DQS\))

Simply clocking data on both edges of \(CK\) is not enough at high speeds because signal propagation delays across the motherboard can cause skew between the clock and the data lines. DDR SDRAM introduces a bidirectional data strobe signal, \(DQS\) (and its complement \(\overline{DQS}\) in newer generations), which travels alongside the \(DQ\) data lines.

  • During a read: The DRAM drives \(DQS\) edge-aligned with the \(DQ\) data bits. The memory controller delays \(DQS\) internally by \(90^\circ\) (a quarter clock cycle) so that its edges land in the center of the data valid window, ensuring reliable sampling.
  • During a write: The memory controller drives \(DQS\) center-aligned with the \(DQ\) data bits, allowing the DRAM to sample the incoming data directly on both the rising and falling edges of \(DQS\).

Delay-Locked Loop (DLL) Synchronization

To keep the outgoing \(DQS\) and \(DQ\) signals tightly aligned with the external \(CK\) and \(\overline{CK}\) inputs despite temperature and voltage variations, DDR SDRAM includes an on-die Delay-Locked Loop (DLL). The DLL continuously measures the phase difference between the internal clock and the external clock, adjusting internal delay lines so that data transitions occur precisely at the expected clock edges.