How Does a Timer Interrupt Return CPU Control to the OS?

A timer interrupt is a hardware signal sent to the central processing unit at regular intervals, forcing it to pause the currently running program and transfer execution to the operating system kernel. This mechanism prevents any single process from monopolizing the processor and enables preemptive multitasking, where the scheduler can decide which task should run next.

Why the Operating System Needs a Timer Interrupt

When a user program runs on the CPU, it executes instructions directly on the hardware. In a cooperative multitasking system, the operating system must wait for the running program to voluntarily yield control through a system call or an explicit yield instruction. If a program enters an infinite loop or simply refuses to yield, the operating system has no way to regain control, and the entire system freezes.

To solve this problem, modern operating systems rely on preemptive multitasking. Preemption requires an external, hardware-enforced mechanism that cannot be ignored or bypassed by user-space software. A programmable hardware timer provides this guarantee by periodically interrupting the CPU regardless of what the current process is doing.

How the Hardware Timer Works

A classical computer system includes a dedicated hardware timer, such as the Programmable Interval Timer (PIT), the Local APIC timer on x86 processors, or the Generic Timer on ARM architectures. During system boot, the operating system configures this timer with a specific countdown value or frequency, often called the tick rate.

For example, if the timer is configured to fire every \(10\text{ ms}\), the tick rate is:

\[f = \frac{1}{0.01\text{ s}} = 100\text{ Hz}\]

Once started, the timer counts down independently of the CPU's instruction stream. When the counter reaches zero, the timer asserts an interrupt request (IRQ) line connected to the processor's interrupt controller, and then resets the counter to begin the next interval.

The Interrupt Handling Sequence

When the CPU receives the timer interrupt signal, it completes the current machine instruction and immediately performs a hardware-enforced context switch into kernel mode. The exact steps vary slightly by architecture, but the core sequence is consistent:

  1. Privilege Escalation: The CPU switches from user mode (low privilege) to kernel mode (high privilege) so that operating system code can access protected hardware and memory structures.
  2. State Preservation: The processor automatically pushes key registers—such as the program counter (instruction pointer), processor status flags, and stack pointer—onto the kernel stack.
  3. Vector Lookup: The CPU uses the interrupt number to look up the corresponding entry in the Interrupt Descriptor Table (IDT) or interrupt vector table.
  4. Handler Execution: Execution jumps to the operating system's timer Interrupt Service Routine (ISR).

Passing Control to the Scheduler

Inside the timer ISR, the operating system performs essential housekeeping. It acknowledges the interrupt to the hardware controller, updates system clocks and process accounting metrics, and checks whether the current process has exhausted its allocated time slice (also known as a quantum).

If the current process still has time remaining and no higher-priority task is waiting, the ISR restores the saved registers and executes a return-from-interrupt instruction, resuming the program exactly where it left off.

If the time slice has expired, the ISR invokes the OS scheduler. The scheduler saves the remaining CPU state (such as general-purpose registers) into the current process's Process Control Block (PCB), selects the next runnable process from the ready queue, loads that process's saved state from its PCB, and returns from the interrupt into the new process. Because this happens tens or hundreds of times per second, multiple programs appear to run simultaneously on a single CPU core.