How Does a Master-Slave D Flip-Flop Work on a Clock Edge?

A master-slave D flip-flop isolates input changes from output transitions by cascading two level-sensitive D latches that are controlled by complementary clock signals. Because only one latch is transparent at any given moment, the input data is captured during one half of the clock cycle and transferred to the output only when the clock transitions to the opposite state. This two-stage mechanism prevents race-through conditions and ensures synchronous state updates in classical digital circuits.

Two-Stage Latch Architecture

A standard master-slave D flip-flop consists of two gated D latches connected in series:

  1. The Master Latch: Receives the external data input \(D\) and is clocked by the primary clock signal \(CLK\) (or \(\overline{CLK}\), depending on edge polarity).
  2. The Slave Latch: Receives the output of the master latch (\(Q_M\)) as its own data input and is clocked by the inverted clock signal \(\overline{CLK}\) (or \(CLK\)).

Because the two latches are driven by opposite phases of the clock, they are never transparent at the same time. When the master latch is open and tracking \(D\), the slave latch is closed and holding the previous state \(Q\). When the slave latch opens to update \(Q\), the master latch is closed and ignoring any further changes on \(D\).

Step-by-Step Operation on a Clock Edge

Consider a positive-edge-triggered master-slave D flip-flop, where the master is active-low (transparent when \(CLK = 0\)) and the slave is active-high (transparent when \(CLK = 1\)):

  1. Setup Phase (\(CLK = 0\)): The master latch is transparent, so its internal node \(Q_M\) continuously follows the input \(D\). Meanwhile, \(\overline{CLK} = 1\) keeps the slave latch disabled (latched), so the final output \(Q\) remains fixed at its previous value. Any fluctuations on \(D\) during this phase are absorbed by the master without affecting \(Q\).
  2. Clock Edge Transition (\(CLK: 0 \rightarrow 1\)): At the rising edge of the clock, the master latch closes and locks in the value of \(D\) that was present just before the edge. Simultaneously, the slave latch becomes transparent, allowing the newly locked value \(Q_M\) to propagate to the output \(Q\).
  3. Hold Phase (\(CLK = 1\)): While the clock remains high, the master latch stays closed. Even if the input \(D\) changes immediately after the rising edge, \(Q_M\) does not change, and therefore \(Q\) remains stable until the next rising clock edge.

Timing Constraints and Isolation

For this isolation to work reliably in classical computing, the input signal \(D\) must satisfy two timing requirements relative to the active clock edge:

  • Setup Time (\(t_{su}\)): The minimum time \(D\) must remain stable before the clock edge so the master latch can reliably capture it.
  • Hold Time (\(t_h\)): The minimum time \(D\) must remain stable after the clock edge while the master latch finishes closing.

Once \(t_h\) has elapsed, the master-slave structure guarantees complete isolation between \(D\) and \(Q\), allowing combinational logic between flip-flops to compute the next state without corrupting the current state.