How Does a Demultiplexer Route a Single Input Signal?
A demultiplexer, often abbreviated as DEMUX, is a combinational logic circuit in classical computing that takes a single data input line and routes it to one of several possible output channels. By using a set of binary select lines, the circuit determines which specific output receives the incoming signal while keeping all other outputs in an inactive state. This article explains the fundamental components of a demultiplexer, how binary addressing controls signal routing, and how logic gates physically implement this distribution.
Core Components of a Demultiplexer
A standard demultiplexer consists of three main types of connections: a single data input, a group of select lines, and multiple output lines. Because the select lines operate using binary logic, the number of output channels is always a power of two relative to the number of select inputs.
If a demultiplexer has \(n\) select lines, it can address up to \(2^n\) distinct output channels. Common configurations include 1-to-2, 1-to-4, 1-to-8, and 1-to-16 demultiplexers. For example, a 1-to-4 demultiplexer requires \(n = 2\) select lines because \(2^2 = 4\).
How Binary Addressing Selects the Output
The select lines act as a binary address that specifies the destination for the data input. Each unique combination of high (\(1\)) and low (\(0\)) voltage levels on the select lines corresponds to a single output channel.
In a 1-to-4 demultiplexer with select lines \(S_1\) and \(S_0\), data input \(D\), and outputs \(Y_0\) through \(Y_3\):
- When \(S_1 = 0\) and \(S_0 = 0\), the binary value is \(00_2\), so \(D\) is routed to \(Y_0\).
- When \(S_1 = 0\) and \(S_0 = 1\), the binary value is \(01_2\), so \(D\) is routed to \(Y_1\).
- When \(S_1 = 1\) and \(S_0 = 0\), the binary value is \(10_2\), so \(D\) is routed to \(Y_2\).
- When \(S_1 = 1\) and \(S_0 = 1\), the binary value is \(11_2\), so \(D\) is routed to \(Y_3\).
At any given moment, only the selected output mirrors the state of \(D\). All unselected outputs remain at a default inactive logic level, typically \(0\).
Logic Gate Implementation
Physically, a demultiplexer is built using AND gates and NOT gates (inverters). Each output channel is driven by its own dedicated AND gate. The data input \(D\) is connected to one input of every AND gate, while the remaining inputs of each AND gate are connected to a unique combination of the select lines and their inverted values.
For a 1-to-4 demultiplexer, the Boolean expressions for each output are:
\[Y_0 = D \cdot \overline{S_1} \cdot \overline{S_0}\] \[Y_1 = D \cdot \overline{S_1} \cdot S_0\] \[Y_2 = D \cdot S_1 \cdot \overline{S_0}\] \[Y_3 = D \cdot S_1 \cdot S_0\]
Because an AND gate outputs \(1\) only when all of its inputs are \(1\), only the gate whose select-line conditions match the current binary address is enabled. For that enabled gate, the output directly follows \(D\). For all other gates, at least one select-line input is \(0\), forcing their outputs to \(0\) regardless of whether \(D\) is \(0\) or \(1\).
Role in Classical Computing Systems
Demultiplexers are essential for resource sharing and data distribution inside digital hardware. In memory systems, they help route data or control signals to specific memory banks or registers. In communication systems, a demultiplexer pairs with a multiplexer at the receiving end of a shared bus, separating time-divided signals back into their original individual channels.