How Do WAR and WAW Name Dependencies Create False Hazards?

Write-after-read and write-after-write name dependencies create false data hazards when two instructions reuse the same register or memory location without actually passing a value between them. In pipelined and out-of-order processors, executing these instructions out of their original program order can overwrite data that an earlier instruction still needs or leave the wrong final value in the shared location. Because the conflict comes from reusing a storage name rather than a true data flow, these hazards are called false hazards and can be eliminated through register renaming.

Understanding Name Dependencies vs. True Data Dependencies

In classical computer architecture, instructions interact through registers and memory. A true data dependency, also known as a read-after-write (RAW) dependency, occurs when instruction \(B\) needs a value computed by instruction \(A\). Instruction \(B\) cannot execute until instruction \(A\) produces its result.

Name dependencies are fundamentally different. They occur when two instructions use the same register or memory address—called a name—even though no data is transferred from the first instruction to the second. Because there is no actual producer-consumer relationship, the dependency is an artifact of limited architectural storage rather than program logic.

Write-After-Read (WAR) Dependencies and Anti-Hazards

A write-after-read (WAR) dependency, also called an anti-dependence, occurs when instruction \(A\) reads from a location and a later instruction \(B\) writes to that same location. In sequential execution, \(A\) reads the old value before \(B\) overwrites it.

In a pipelined or out-of-order processor, instruction \(B\) might be ready to execute and write its result before instruction \(A\) has finished reading the operand. If \(B\) writes early, \(A\) will read the newly written value instead of the original value, causing a WAR hazard and producing an incorrect result.

Consider the following sequence:

1: ADD R1, R2, R3   ; R1 = R2 + R3 (reads R2)
2: SUB R2, R4, R5   ; R2 = R4 - R5 (writes R2)

Instruction 2 writes to R2 after instruction 1 reads R2. If instruction 2 completes its writeback stage before instruction 1 reads R2, the ADD instruction will use the wrong value of R2.

Write-After-Write (WAW) Dependencies and Output Hazards

A write-after-write (WAW) dependency, also called an output dependence, occurs when two instructions write to the same register or memory location. In sequential execution, the second write must happen last so that subsequent instructions see the newer value.

If a processor executes instructions out of order or has pipelines of different lengths, the second instruction might finish and write its result before the first instruction writes its result. When the first instruction eventually writes, it overwrites the newer value with an older one, creating a WAW hazard.

Consider this example:

1: MUL R1, R2, R3   ; R1 = R2 * R3 (writes R1, long latency)
2: ADD R1, R4, R5   ; R1 = R4 + R5 (writes R1, short latency)

Multiplication typically takes more clock cycles than addition. If ADD finishes and writes to R1 first, and MUL writes to R1 later, R1 will hold the product instead of the sum, violating program semantics.

Eliminating False Hazards with Register Renaming

Because WAR and WAW dependencies do not represent true data flow, processors can remove them without changing program behavior. The standard hardware technique for doing this is register renaming.

Modern out-of-order processors maintain a pool of physical registers that is larger than the set of architectural registers exposed to the instruction set. When instructions are decoded, the processor maps each architectural destination register to a fresh physical register.

Applying register renaming to the earlier WAR example gives:

1: ADD P1, P2, P3   ; P1 = P2 + P3
2: SUB P6, P4, P5   ; P6 = P4 - P5

Here, R2 for the ADD instruction remains mapped to P2, while the SUB instruction writes to a newly allocated physical register P6. Both instructions can now execute in parallel or out of order without any risk of overwriting P2. The same mechanism resolves WAW hazards by giving each write its own distinct physical destination register.