How Do Verilog and VHDL Model Concurrent Hardware Timing?

Hardware description languages such as Verilog and VHDL model concurrent hardware timing by treating a digital circuit as a network of independent, simultaneously operating processes rather than a single sequence of instructions. Instead of executing one line after another like classical software, these languages use event-driven simulation, sensitivity lists, and discrete time steps to represent how physical logic gates, wires, and flip-flops react to electrical signals at the same time.

Concurrency Versus Sequential Execution

In classical software languages like C or Python, a program counter steps through instructions one by one. Even when multithreading is used, threads are typically scheduled by an operating system onto a limited number of processor cores.

Digital hardware works differently. Every logic gate, multiplexer, and register on a silicon chip is physically present and active simultaneously. When a voltage changes on an input wire, every gate connected to that wire begins evaluating its output at the exact same moment.

HDLs capture this physical reality through concurrent constructs:

  • Continuous assignments: Statements like assign in Verilog or concurrent signal assignments in VHDL remain permanently active, continuously driving a wire whenever any input changes.
  • Parallel processes: Blocks such as always in Verilog and process in VHDL represent independent hardware blocks that all run concurrently with one another.
  • Structural instantiation: Connecting modules or components together mirrors wiring physical chips on a circuit board, where all components operate in parallel.

Event-Driven Simulation and Sensitivity Lists

To simulate millions of concurrent hardware elements on a sequential CPU, HDL simulators use an event-driven model. Rather than evaluating every gate at every picosecond, the simulator maintains an event queue ordered by simulation time.

Each concurrent process has a sensitivity list, which specifies the signals that can trigger it to re-evaluate. For example, a combinational logic block is sensitive to all of its inputs, while a synchronous flip-flop is typically sensitive only to a clock edge. When a signal changes value, an event is scheduled. The simulator advances to the next scheduled time, updates the signal, and wakes up only the processes that are sensitive to that signal.

Delta Cycles and Zero-Time Ordering

Because multiple processes can react to the same event at the exact same simulation timestamp \(t\), simulators need a way to resolve cause-and-effect without advancing physical time. They do this using delta cycles.

A delta cycle is an infinitesimally small step in simulation time, often denoted as \(\Delta t\). If Process A updates a signal at time \(t\), and Process B reads that signal, Process B is scheduled to execute at \(t + \Delta t\). Simulation time \(t\) does not advance until all delta cycles at that timestamp are resolved and the circuit reaches a steady state.

This mechanism prevents race conditions in combinational feedback loops and ensures deterministic behavior when signals propagate through multiple layers of zero-delay logic.

Blocking vs. Non-Blocking Assignments

HDLs also distinguish between immediate updates and scheduled updates to model sequential storage elements like flip-flops accurately:

  • Signal / Non-blocking assignments (<=): In both VHDL signals and Verilog non-blocking assignments, the right-hand side is evaluated immediately, but the left-hand side is not updated until the end of the current delta cycle. This models flip-flops sampling their inputs on a clock edge without interfering with other flip-flops reading the old values at the same edge.
  • Variable / Blocking assignments (= or :=): These update immediately, behaving like traditional software variables. They are primarily used for intermediate calculations inside a single process or combinational logic.

Modeling Physical Propagation Delays

Real hardware is not instantaneous; signals take time to travel through transistors and wires. HDLs allow designers to model this explicitly using delay annotations, such as #5 in Verilog or after 5 ns in VHDL.

Simulators support different delay models:

  • Inertial delay: Filters out pulses shorter than the gate's propagation delay, modeling how physical transistors cannot switch faster than their RC time constant.
  • Transport delay: Passes all pulses through unchanged after a fixed time offset, modeling ideal transmission lines or wires.

When a circuit is synthesized into actual silicon or an FPGA, these explicit simulation delays are ignored. Instead, static timing analysis tools calculate the true physical delays from the layout and verify that signals arrive before the next clock edge.