How Do UART Peripherals Frame Serial Bytes Without a Clock?
Universal Asynchronous Receiver-Transmitter peripherals transmit and receive serial data over a single wire per direction without a shared clock signal by wrapping each byte in a standardized frame of start, data, parity, and stop bits. Because there is no clock line to tell the receiver when to sample each bit, both devices must agree in advance on a transmission speed, known as the baud rate, and rely on voltage transitions at the start of every frame to synchronize their internal timers.
Asynchronous Timing and Idle State
In an asynchronous serial link, the transmitter and receiver operate on independent local oscillators. When no data is being sent, the line is held at a logic high voltage, called the mark state. Holding the line high during idle periods allows the receiver to distinguish between an inactive line and the beginning of a transmission, as well as detect a disconnected wire if the line drops to zero volts indefinitely.
Both sides must be configured to the same baud rate, which defines the duration of a single bit period \(T_{\text{bit}}\):
\[T_{\text{bit}} = \frac{1}{\text{Baud Rate}}\]
For example, at \(9600\text{ baud}\), each bit lasts approximately \(104.17\text{ }\mu\text{s}\).
The Start Bit and Synchronization
Every UART frame begins with a start bit. To initiate a transfer, the transmitter pulls the line from the idle high state to a logic low state, called the space state, for one bit period.
This high-to-low falling edge serves as the synchronization trigger for the receiver. Upon detecting the falling edge, the receiver starts an internal counter, typically oversampling the incoming line at \(16\times\) the configured baud rate. By waiting half a bit period (\(8\) oversample ticks) to verify the line is still low, the receiver confirms it has found a valid start bit rather than a brief noise spike, and aligns its sampling point to the center of every subsequent bit in the frame.
Data Bits
Immediately following the start bit, the transmitter sends the payload data bits. Classical UART hardware supports \(5\) to \(9\) data bits per frame, with \(8\) bits being the standard for modern byte-oriented communication.
UART transmits data least significant bit (LSB) first. For instance,
the ASCII character A (\(0\text{x}41\), or 01000001 in
binary) is placed on the wire in the order
1, 0, 0, 0, 0, 0, 1, 0.
The Optional Parity Bit
After the data bits, the frame may include a single parity bit for basic error detection. Parity is configured as either even, odd, or none:
- Even parity: The parity bit is set so that the
total number of
1bits in the data plus the parity bit is even. - Odd parity: The parity bit is set so that the total
number of
1bits in the data plus the parity bit is odd.
If electrical noise flips a single bit during transmission, the receiver's calculated parity will not match the received parity bit, and the UART peripheral flags a parity error. However, a single parity bit cannot detect an even number of simultaneous bit flips.
Stop Bits and Frame Completion
The frame concludes with one or more stop bits, during which the transmitter drives the line back to the logic high (mark) state. Classical UARTs support \(1\), \(1.5\), or \(2\) stop bits.
Stop bits serve two purposes. First, they give the receiver's hardware a brief recovery window to transfer the assembled byte into a receive buffer before the next frame arrives. Second, because the stop bit is always high and the next start bit is always low, the line is guaranteed to have a falling edge at the start of the following byte, even if the preceding data bits ended with zeros. If the receiver samples a logic low where a stop bit should be, it flags a framing error, indicating clock drift or a baud rate mismatch.
Clock Drift Tolerance
Because the receiver resynchronizes on every start bit, small frequency differences between the transmitter and receiver oscillators do not accumulate across multiple bytes. Over a standard \(10\)-bit frame (\(1\) start bit, \(8\) data bits, \(1\) stop bit), the combined clock error must remain small enough that the final stop bit is still sampled within its valid window, typically allowing a total clock mismatch of up to roughly \(\pm 2\%\) to \(\pm 3\%\).