How Do Structural Hazards Occur in a CPU Pipeline?

A structural hazard occurs in a pipelined processor when two or more instructions in different pipeline stages require the same hardware functional unit during the same clock cycle. Because a single physical resource cannot simultaneously serve two independent operations without corrupting data or losing control signals, the processor must stall one of the instructions until the resource becomes available.

Understanding Instruction Pipelining

In classical computing, instruction pipelining increases throughput by overlapping the execution of multiple instructions. A standard five-stage RISC pipeline divides instruction processing into Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). Ideally, one instruction completes every clock cycle, yielding a Cycles Per Instruction (CPI) close to \(1\).

However, this ideal throughput assumes that every pipeline stage has dedicated hardware resources. When hardware is shared across stages to reduce chip area, cost, or power consumption, resource conflicts arise.

Common Causes of Structural Hazards

Structural hazards typically appear in three main scenarios within a processor's microarchitecture:

  1. Unified Memory: If a processor uses a single memory unit for both instructions and data (a von Neumann architecture), a conflict occurs whenever one instruction is in the MEM stage (reading or writing data) while a later instruction is in the IF stage (fetching the next instruction). Both stages need the memory bus in the same clock cycle.
  2. Shared Register File Ports: The ID stage reads source registers while the WB stage writes results back to the register file. If the register file does not have enough independent read and write ports, these two stages will collide.
  3. Non-Pipelined Functional Units: Complex operations such as floating-point division or multiplication often use a single, unpipelined execution unit that takes multiple clock cycles to complete. If a second instruction needs that same unit before the first finishes, a structural hazard occurs.

Impact on Pipeline Performance

When a structural hazard is detected, the pipeline control logic inserts a stall (often called a bubble) into the later instruction's stage, delaying it by one or more clock cycles. This directly increases the average CPI:

\[\text{CPI}_{\text{actual}} = \text{CPI}_{\text{ideal}} + \text{Stall Cycles per Instruction}\]

Even a small fraction of instructions causing stalls can noticeably degrade overall processor performance.

How Processors Resolve Structural Hazards

Hardware designers eliminate or mitigate structural hazards using several well-established techniques:

  • Resource Duplication: Splitting unified memory into separate instruction and data caches (a modified Harvard architecture) allows the IF and MEM stages to operate simultaneously without conflict.
  • Multi-Ported Components: Designing register files with dedicated read ports for the ID stage and dedicated write ports for the WB stage prevents register access collisions.
  • Pipelining Functional Units: Breaking multi-cycle execution units (like floating-point adders) into smaller, pipelined sub-stages allows a new operation to enter the unit every clock cycle.
  • Pipeline Stalling: When duplicating hardware is too expensive, the control unit simply stalls the conflicting stage for one or more cycles until the shared functional unit is free.