How Do Row Buffer Hits and Misses Affect DRAM tRCD Latency?

Row buffer hits and misses directly determine whether a memory access incurs the row address strobe to column address strobe delay, known as tRCD, in dynamic random-access memory. A row buffer hit bypasses this delay entirely because the target row is already open in the sense amplifiers, whereas a row buffer miss forces the memory controller to open a new row and wait for the full tRCD duration before reading or writing data.

Understanding Row Buffers and tRCD

In classical computing systems, main memory is typically built from DRAM organized into banks, rows, and columns. Each bank contains a row buffer, which is an array of sense amplifiers that holds the contents of the most recently activated row.

When a processor requests data from a memory address, the memory controller translates that address into a bank, row, and column. Before any column can be read or written, the corresponding row must be copied into the row buffer. The time required to activate a row—moving its data from the memory cells into the sense amplifiers—and make it ready for a column command is called the row address strobe to column address strobe delay, written as \(t_{\text{RCD}}\).

What Happens During a Row Buffer Hit

A row buffer hit occurs when a memory request targets a row that is already loaded in the bank's row buffer. Because the data is already present in the sense amplifiers, the memory controller does not need to issue a row activation command.

As a result, the \(t_{\text{RCD}}\) latency is completely avoided. The controller can immediately issue a column read or write command, meaning the access only incurs the column address strobe latency (\(t_{\text{CL}}\) or \(t_{\text{CAS}}\)) plus any bus transfer time. This makes row buffer hits the fastest possible DRAM access pattern.

What Happens During a Row Buffer Miss

A row buffer miss—often divided into a row buffer empty (cold miss) and a row buffer conflict—occurs when the requested row is not currently in the row buffer.

1. Row Buffer Empty: If no row is currently open in the bank, the memory controller issues an Activate (ACT) command for the target row. It must then wait for \(t_{\text{RCD}}\) before issuing the column command. The total command-to-data latency is \(t_{\text{RCD}} + t_{\text{CL}}\).
2. Row Buffer Conflict: If a different row is currently open in the bank, the controller must first close that row using a Precharge (PRE) command, which takes row precharge time (\(t_{\text{RP}}\)). Only after precharging completes can the controller activate the new row and wait for \(t_{\text{RCD}}\), followed by \(t_{\text{CL}}\). The total latency becomes \(t_{\text{RP}} + t_{\text{RCD}} + t_{\text{CL}}\).

Impact on System Performance

Because \(t_{\text{RCD}}\) and \(t_{\text{RP}}\) each typically take tens of nanoseconds—comparable to dozens of CPU clock cycles—row buffer misses significantly increase memory access latency. Workloads with high spatial locality, such as sequential array traversals, achieve high row buffer hit rates and avoid \(t_{\text{RCD}}\) penalties. Conversely, workloads with random or strided access patterns that jump between different rows suffer frequent misses and conflicts, repeatedly paying the full \(t_{\text{RCD}}\) cost and reducing overall memory bandwidth efficiency.