How Do Priority Encoders Resolve Simultaneous Inputs?
Priority encoders resolve simultaneous active inputs by assigning a fixed hierarchy to every input line and outputting the binary code of only the highest-priority active request. When multiple hardware devices assert their request lines at the exact same clock cycle, combinational logic gates inside the encoder mask out all lower-priority signals so that the processor or bus arbiter receives a single, unambiguous binary address.
The Problem of Simultaneous Hardware Requests
In classical computing systems, multiple peripherals—such as timers, disk controllers, and network interfaces—often share a single interrupt controller or system bus. A standard binary encoder assumes that only one input line is active at any given time. If two or more devices send an active signal simultaneously, a standard encoder produces a corrupted output, typically the bitwise OR of their binary addresses. Priority encoders eliminate this ambiguity by enforcing a deterministic ranking among all input lines.
Fixed Priority Hierarchy and Masking Logic
A \(2^n\)-to-\(n\) priority encoder accepts \(2^n\) input lines, commonly labeled \(D_0\) through \(D_{2^n - 1}\), and produces an \(n\)-bit binary output. In most standard designs, higher-indexed inputs carry higher priority, meaning \(D_3\) takes precedence over \(D_2\), \(D_1\), and \(D_0\) in a 4-to-2 encoder.
To resolve simultaneous requests, the internal combinational circuit
uses AND, OR, and NOT gates to
disable lower-priority inputs whenever a higher-priority input is
active. For a 4-to-2 priority encoder with active-high inputs (\(D_3\) highest, \(D_0\) lowest) and outputs \(Y_1\) and \(Y_0\), the Boolean expressions are:
\[Y_1 = D_3 + D_2\]
\[Y_0 = D_3 + (\overline{D_2} \cdot D_1)\]
Notice that \(D_0\) does not appear
in either equation; when \(D_0\) is the
only active input, both \(Y_1\) and
\(Y_0\) evaluate to \(0\), representing the binary value
00. If \(D_3\) and \(D_1\) are active at the same time, \(D_3\) forces both \(Y_1 = 1\) and \(Y_0 = 1\) (binary 11),
completely ignoring \(D_1\).
The Valid Output Indicator
Because 00 represents both "input \(D_0\) is active" and "no inputs are
active," priority encoders include an additional output bit called the
valid indicator (\(V\)). The valid bit
is asserted whenever at least one input line is active:
\[V = D_3 + D_2 + D_1 + D_0\]
Downstream hardware, such as a CPU interrupt controller, checks \(V\) before reading the encoded address. If \(V = 0\), the system knows no hardware requests are pending.
Handling Hardware Requests in Practice
In real-world systems, priority encoders are commonly used in:
- Interrupt Controllers: Ranking hardware interrupts so critical events, such as power-failure warnings or system timers, preempt less urgent tasks like keyboard input.
- Bus Arbitration: Granting access to a shared memory or data bus when multiple DMA controllers or processor cores request it simultaneously.
- Cascading Encoders: Combining smaller priority encoders (such as 8-to-3 chips) using enable-in and enable-out pins to manage 16, 32, or more hardware request lines without losing deterministic priority.