How do load-store architectures restrict memory access?

Load-store architectures enforce a strict separation between data processing and memory access at the instruction set and hardware levels. In classical computing, this design ensures that arithmetic, logic, and control-flow instructions operate exclusively on CPU registers, while only dedicated load and store instructions can read from or write to main memory.

Instruction Set Architecture (ISA) Constraints

The primary mechanism that restricts memory access is the design of the instruction set itself. In a load-store architecture, such as RISC-V, ARM, or MIPS, the instruction formats for computational operations do not include fields for memory addresses or memory addressing modes.

  • Register-only operands: Arithmetic and logic instructions (such as ADD, SUB, or AND) only encode register identifiers (e.g., rd, rs1, rs2) or immediate constants. There is no bit-level encoding available to specify a memory location.
  • Dedicated memory instructions: Only explicit load instructions (such as LW or LDR) and store instructions (such as SW or STR) contain the opcodes and addressing fields—typically a base register plus an offset—needed to reference main memory.

Because the ISA provides no way to encode a memory operand inside an ALU instruction, programs are structurally incapable of performing direct memory-to-memory or register-to-memory arithmetic.

Datapath and Pipeline Separation

The hardware datapath mirrors this ISA restriction by physically isolating the Arithmetic Logic Unit (ALU) from the memory interface.

  1. Register file as the sole ALU source: The inputs to the ALU are wired exclusively to the outputs of the general-purpose register file (and immediate-value generators). The ALU cannot directly receive data from the data cache or system bus.
  2. Dedicated memory stage: In a classic five-stage pipeline (Instruction Fetch, Instruction Decode, Execute, Memory Access, Write Back), the Memory Access stage is only active for load and store instructions. For all other instructions, this stage is bypassed.
  3. Address calculation: During the Execute stage, load and store instructions use the ALU to compute the effective memory address, typically expressed as \(\text{Effective Address} = \text{Base Register} + \text{Offset}\). That computed address is then passed to the memory subsystem.

Control Unit Enforcement

The CPU's control unit decodes each instruction's opcode and generates the control signals that govern the datapath. Hardware-level enforcement relies on these signals:

  • Memory Read (MemRead) and Memory Write (MemWrite): These control lines are only asserted when the decoded opcode belongs to a load or store instruction, respectively.
  • Multiplexer routing: Control signals configure multiplexers at the write-back stage so that only a load instruction routes data from memory into the register file, whereas ALU instructions route the ALU's output back to the register file.

If an instruction is not a load or store, the memory interface remains idle during its execution, preventing any unintended memory bus transactions.

Advantages of Strict Separation

Restricting memory access to dedicated instructions simplifies processor design and improves execution predictability:

  • Uniform instruction length: Without variable-length memory addressing modes in every instruction, instructions can be fixed-width (commonly 32 bits), simplifying instruction fetch and decode.
  • Simplified pipelining: Separating memory latency from arithmetic execution makes pipeline hazards easier to manage and reduces structural conflicts.
  • Predictable timing: Register-to-register operations complete in a consistent number of cycles, whereas variable-latency memory operations are isolated to explicit load and store instructions.