How Do Intel UPI and AMD Infinity Fabric Link Processor Dies?

Modern high-performance processors rely on multiple silicon dies rather than a single monolithic chip to scale core counts and improve manufacturing yields. Intel Ultra Path Interconnect and AMD Infinity Fabric are the specialized interconnect architectures that bind these separate dies into a unified, cache-coherent computing system. By managing high-speed point-to-point data transfers, memory access, and cache coherency protocols across physical boundaries, both technologies allow operating systems and applications to treat a multi-die or multi-socket machine as a single logical processor.

Why Multi-Die Architectures Need High-Speed Interconnects

As transistor scaling slowed and reticle limits constrained the maximum size of a single silicon die, chipmakers shifted toward chiplet and multi-die designs. Splitting a processor into smaller dies reduces manufacturing defects and lowers costs, but it introduces a major engineering challenge: communication between cores on different dies must be fast enough to avoid bottlenecks.

Without a dedicated interconnect, a core on one die trying to read data cached on another die would suffer severe latency penalties. Both Intel Ultra Path Interconnect (UPI) and AMD Infinity Fabric solve this by providing high-bandwidth, low-latency pathways that maintain a single shared memory address space across all dies.

How Intel Ultra Path Interconnect (UPI) Works

Intel Ultra Path Interconnect, introduced with the Skylake-SP Xeon architecture to replace the older QuickPath Interconnect (QPI), is a point-to-point processor interconnect designed primarily for multi-socket servers and multi-die Xeon packages.

Point-to-Point Topology and Packet Routing

UPI links processors directly using dedicated high-speed serial lanes. Each UPI link consists of multiple differential pairs for transmitting and receiving data simultaneously. Rather than broadcasting every request to all nodes, UPI uses a directory-based coherency protocol. A home agent tracks which cache lines are owned by which die or socket, routing snoop requests only where needed to minimize wasted bandwidth.

Cache Coherency and NUMA

When a core requests data not present in its local L1, L2, or L3 cache, the memory controller or caching agent checks the directory. If the data resides in a remote die's cache or local DRAM, UPI transfers the cache line across the link. Because accessing memory attached to a remote die takes longer than accessing local memory, systems using UPI expose Non-Uniform Memory Access (NUMA) domains to the operating system so schedulers can keep threads close to their data.

How AMD Infinity Fabric Works

AMD Infinity Fabric is a modular, scalable interconnect architecture used across Ryzen, Threadripper, and EPYC processors. Unlike UPI, which was initially focused on socket-to-socket links, Infinity Fabric was built from the ground up to connect chiplets within a single package as well as across multiple sockets.

Control Fabric and Data Fabric

Infinity Fabric is divided into two distinct planes:

• Scalable Data Fabric (SDF): Handles the actual movement of data packets between CPU Core Complex Dies (CCDs), I/O dies, memory controllers, and PCIe lanes.
• Scalable Control Fabric (SCF): Manages system-level functions such as power management, thermal monitoring, clock distribution, and security resets across all connected dies.

Chiplet-to-I/O Die Communication

In modern AMD EPYC and Ryzen architectures, compute cores reside on separate CCDs fabricated on leading-edge process nodes, while memory controllers and I/O interfaces sit on a central I/O die (IOD). Infinity Fabric links each CCD to the central IOD using high-speed, low-power SerDes (Serializer/Deserializer) or advanced packaging traces. Because all memory traffic flows through the central IOD, latency between cores on different CCDs remains uniform, simplifying memory scheduling compared to older multi-die designs.

Key Architectural Differences

While both interconnects achieve cache-coherent multi-die communication, they differ in how they scale and route traffic:

• Primary Scope: Intel UPI is predominantly used for socket-to-socket communication and connecting large compute tiles, whereas AMD Infinity Fabric serves as a universal fabric for intra-package chiplet links, inter-socket links, and even GPU-to-CPU connections (Infinity Fabric Links).
• Clocking and Bandwidth: Earlier generations of Infinity Fabric tied its clock speed directly to the system memory clock (\(f_{\text{IF}} = f_{\text{MCLK}}\)), though newer architectures allow decoupled ratios. Intel UPI operates independently of the memory clock, using fixed high-speed link rates measured in gigatransfers per second (\(\text{GT/s}\)).
• Topology: UPI typically forms direct mesh or ring topologies between sockets, while Infinity Fabric uses a hub-and-spoke layout inside the package (CCDs to I/O die) and point-to-point links between sockets.

Performance Trade-Offs in Classical Computing

In classical computing workloads, the performance of both interconnects depends on bandwidth, hop count, and latency. If a workload frequently shares data between threads running on different dies, interconnect saturation or cross-die latency can reduce scaling efficiency.

Total theoretical unidirectional bandwidth per link can be expressed as:

\[\text{Bandwidth} = \text{Link Rate} \times \text{Lane Width} \times \text{Encoding Efficiency}\]

To mitigate cross-die penalties, modern compilers, hypervisors, and operating systems use NUMA-aware scheduling. By pinning related threads and their allocated memory pages to the same die or socket, systems minimize the volume of traffic traversing UPI or Infinity Fabric, reserving interconnect bandwidth for genuinely shared workloads.