How Do FPGAs Implement Custom Digital Logic?

Field-Programmable Gate Arrays implement custom digital logic by combining arrays of configurable logic blocks with a programmable interconnect fabric. Instead of fabricating fixed silicon gates for a specific circuit, an FPGA uses small memory-based lookup tables to emulate any Boolean function and a routing matrix of programmable switches to wire those functions together. This architecture allows hardware engineers to reconfigure the physical behavior of the chip after manufacturing by loading a binary configuration file.

Configurable Logic Blocks and Lookup Tables

The fundamental building block of an FPGA is the Configurable Logic Block (CLB), which contains one or more Lookup Tables (LUTs) paired with storage elements. A LUT is essentially a small, fast Static Random-Access Memory (SRAM) array combined with a multiplexer tree. Rather than using physical AND, OR, or NOT gates, a \(k\)-input LUT stores the complete truth table for any Boolean function of \(k\) variables.

Because a \(k\)-input Boolean function has \(2^k\) possible input combinations, a \(k\)-input LUT requires \(2^k\) bits of configuration memory. For example, a 4-input LUT stores \(2^4 = 16\) bits, while a modern 6-input LUT stores \(2^6 = 64\) bits. When signals arrive at the \(k\) input pins of the LUT, they act as select lines for the multiplexer, which routes the single corresponding bit from the SRAM to the LUT output.

For instance, to implement the 3-input Boolean function \(Y = (A \cdot B) + \overline{C}\), the synthesis tool precomputes the 8 output bits for every combination of \((A, B, C)\) and writes them into the LUT's SRAM. During operation, the LUT evaluates \(Y\) in constant time, regardless of the function's complexity, because the signal simply traverses a fixed multiplexer depth.

Flip-Flops and Sequential Logic

Combinational logic alone cannot store state or synchronize operations across clock cycles. To support sequential circuits such as finite state machines, counters, and pipelines, each LUT in a CLB is typically paired with a D-type flip-flop.

A multiplexer at the output of the logic slice determines whether the LUT's result goes directly to the routing fabric (combinational path) or is registered by the flip-flop on a clock edge (sequential path). This tight coupling between LUTs and flip-flops minimizes propagation delay and enables high-frequency synchronous designs.

Programmable Routing Matrices

While LUTs provide the computation, the programmable routing matrix provides the communication. An FPGA's logic blocks are arranged in a two-dimensional grid surrounded by horizontal and vertical routing channels filled with metal wire segments of varying lengths.

At the intersections of these channels sit programmable switch matrices. Each switch matrix contains arrays of pass transistors or multiplexers controlled by configuration SRAM bits. By turning specific switches on or off, the FPGA connects the output of one CLB to the inputs of another, forming custom data paths across the chip.

Because routing signals through programmable switches introduces resistance and capacitance, interconnect delay often dominates the critical path timing of an FPGA design. Modern architectures mitigate this by providing a hierarchy of wire lengths, including:

  • Direct local connections between adjacent CLBs for fast carry chains and tight loops
  • Medium-length lines spanning several logic blocks
  • Long global lines and dedicated clock networks for low-skew distribution across the entire die

From Hardware Description to Bitstream

Implementing a custom circuit on an FPGA requires translating a high-level Hardware Description Language (HDL) design, such as Verilog or VHDL, into a physical configuration:

  1. Synthesis: The toolchain converts RTL code into a netlist of generic logic gates and registers.
  2. Technology Mapping: The netlist is grouped and packed into \(k\)-input LUTs and flip-flops specific to the target FPGA architecture.
  3. Place and Route: The placer assigns each mapped LUT and flip-flop to a physical CLB location, and the router determines which switch matrix paths will connect them while meeting timing constraints.
  4. Bitstream Generation: The final placement and routing decisions are compiled into a binary bitstream that initializes every LUT SRAM cell and routing switch on the device.

Once the bitstream is loaded into the FPGA's configuration memory, the hardware immediately behaves as the specified digital circuit, executing operations in true parallel hardware rather than sequentially fetching instructions like a processor.