How Do Cross-Coupled Gates Store State in an SR Latch?

An SR latch stores a single bit of data using two cross-coupled logic gates, either NOR or NAND, connected in a feedback loop. Because the output of each gate feeds directly into the input of the other, the circuit settles into one of two stable states, representing a binary 0 or 1, and holds that value even after the input signals return to their idle levels.

The Principle of Bistability and Feedback

In classical digital logic, a bistable circuit is one that has two stable equilibrium states. Unlike combinational logic circuits, whose outputs depend solely on their current inputs, an SR (Set-Reset) latch is a sequential circuit that exhibits memory.

This memory is achieved through positive feedback. By routing the output \(Q\) of the first gate to an input of the second gate, and the complementary output \(\overline{Q}\) of the second gate back to an input of the first gate, the two gates continuously reinforce each other's state. Once the circuit is driven into either \(Q = 1\) (with \(\overline{Q} = 0\)) or \(Q = 0\) (with \(\overline{Q} = 1\)), the feedback loop locks the outputs in place until a new input pulse forces a transition.

Active-High NOR Gate SR Latch

A NOR-based SR latch uses two cross-coupled NOR gates with active-high inputs, meaning a logic \(1\) triggers a state change and \(0\) is the idle state. The Boolean expressions for the outputs are:

\[Q = \overline{R + \overline{Q}}\]

\[\overline{Q} = \overline{S + Q}\]

When both inputs are idle (\(S = 0, R = 0\)), the latch holds its previous state:

• Holding \(Q = 1\): If \(Q = 1\), that \(1\) feeds into the bottom NOR gate alongside \(S = 0\), forcing \(\overline{Q} = \overline{0 + 1} = 0\). This \(0\) feeds back into the top NOR gate alongside \(R = 0\), yielding \(Q = \overline{0 + 0} = 1\). The state is self-sustaining.
• Holding \(Q = 0\): If \(Q = 0\) and \(\overline{Q} = 1\), the top NOR gate sees \(R = 0\) and \(\overline{Q} = 1\), keeping \(Q = 0\). The bottom NOR gate sees \(S = 0\) and \(Q = 0\), keeping \(\overline{Q} = 1\).

Applying \(S = 1, R = 0\) forces \(\overline{Q} = 0\), which in turn forces \(Q = 1\) (setting the latch). Applying \(S = 0, R = 1\) forces \(Q = 0\), which forces \(\overline{Q} = 1\) (resetting the latch). If both \(S = 1\) and \(R = 1\) are applied simultaneously, both outputs are forced to \(0\), violating the complementary relationship \(Q \neq \overline{Q}\) and creating an invalid state.

Active-Low NAND Gate SR Latch

A NAND-based SR latch (often denoted as an \(\overline{S}\overline{R}\) latch) uses two cross-coupled NAND gates with active-low inputs, meaning a logic \(0\) triggers a state change and \(1\) is the idle state. The governing equations are:

\[Q = \overline{\overline{S} \cdot \overline{Q}}\]

\[\overline{Q} = \overline{\overline{R} \cdot Q}\]

When both inputs are idle (\(\overline{S} = 1, \overline{R} = 1\)), the latch maintains its stored bit:

• Holding \(Q = 1\): With \(Q = 1\) and \(\overline{R} = 1\), the bottom NAND gate outputs \(\overline{Q} = \overline{1 \cdot 1} = 0\). That \(0\) feeds into the top NAND gate with \(\overline{S} = 1\), producing \(Q = \overline{1 \cdot 0} = 1\).
• Holding \(Q = 0\): With \(Q = 0\) and \(\overline{R} = 1\), the bottom NAND gate outputs \(\overline{Q} = 1\). That \(1\) feeds into the top NAND gate with \(\overline{S} = 1\), keeping \(Q = 0\).

Pulling \(\overline{S} = 0\) while \(\overline{R} = 1\) sets \(Q = 1\), while pulling \(\overline{R} = 0\) while \(\overline{S} = 1\) resets \(Q = 0\). Pulling both inputs low (\(\overline{S} = 0, \overline{R} = 0\)) forces both \(Q\) and \(\overline{Q}\) to \(1\), which is the forbidden state for a NAND latch.

Summary of SR Latch Behavior

The following table compares the operational states of NOR and NAND SR latches:

Through this simple cross-coupled feedback architecture, classical computers build the foundational 1-bit memory cells used in registers, flip-flops, and static random-access memory (SRAM).