How Do ACPI Tables Manage Hardware and Sleep States?

Advanced Configuration and Power Interface tables act as a standardized bridge between system firmware and the operating system in classical computing. Stored in memory during boot, these data structures describe the physical hardware layout, interrupt routing, and power management capabilities of a machine so the kernel can configure devices and transition between active and low-power sleep states without relying on hardcoded motherboard drivers.

The Role of Firmware and Boot Discovery

When a classical computer powers on, the firmware, typically UEFI or legacy BIOS, initializes the processor, memory controller, and core buses before handing control to the operating system. Because x86 and many ARM server platforms vary widely in how components are wired together, the operating system cannot assume fixed memory addresses or interrupt lines for every device.

To solve this, the firmware constructs a set of ACPI tables in a reserved region of physical RAM. The operating system locates these tables by finding the Root System Description Pointer, known as the RSDP. On UEFI systems, the firmware passes the RSDP address directly to the bootloader through the EFI System Table. On legacy BIOS systems, the kernel scans specific regions of low memory for the RSDP signature.

The RSDP points to the Extended System Description Table, or XSDT, which serves as a master directory containing 64-bit physical addresses for all other ACPI tables in the system.

Discovering Hardware Topology

ACPI tables separate static hardware descriptions from dynamic device control. Several key tables work together to map out the hardware topology:

  • Multiple APIC Description Table (MADT): Describes the interrupt architecture of the system. It lists every local Advanced Programmable Interrupt Controller (APIC) for each CPU core, as well as I/O APICs and interrupt source overrides that map legacy ISA interrupts to modern interrupt lines.
  • Static Resource Affinity Table (SRAT): Defines memory and processor affinity in Non-Uniform Memory Access (NUMA) systems. It tells the kernel which CPU cores belong to which physical sockets and which ranges of RAM are local to each socket, allowing the scheduler to minimize cross-socket memory latency.
  • System Locality Distance Information Table (SLIT): Provides a matrix of relative memory access latencies between different NUMA nodes.
  • PCI Express Memory Mapped Configuration Space (MCFG): Supplies the base physical addresses for PCIe configuration space, enabling the operating system to enumerate PCIe buses, bridges, and endpoints.

For devices that are not self-enumerating like PCIe, such as embedded controllers, fans, thermal sensors, and motherboard-integrated buses, the firmware provides the Differentiated System Description Table (DSDT) and Secondary System Description Tables (SSDTs).

AML and the ACPI Namespace

Unlike the static tables above, the DSDT and SSDTs contain bytecode written in ACPI Machine Language (AML). The operating system includes an AML interpreter inside the kernel, such as ACPICA in Linux or the Windows ACPI driver.

When the kernel parses the DSDT and SSDTs, it builds a hierarchical tree in memory called the ACPI Namespace. Each node in this tree represents a physical device, bus, power resource, or thermal zone. Devices are identified by standardized hardware IDs, such as _HID and _CID, which tell the operating system which device driver to load. Control methods written in AML, such as _CRS (Current Resource Settings) and _PRS (Possible Resource Settings), allow the kernel to query which I/O ports, memory ranges, and interrupts a device uses or can be assigned.

Managing Sleep States

ACPI defines a set of global and system sleep states, ranging from \(S0\) (fully working) to \(S5\) (soft off). The intermediate states allow the system to trade wake-up latency for power savings:

  • \(S0ix\) (Modern Standby): A low-power idle state where the CPU enters deep package C-states while keeping memory active and the system capable of waking instantly.
  • \(S1\): The CPU stops executing instructions, and CPU caches are flushed, while power to the CPU and RAM is maintained.
  • \(S3\) (Suspend to RAM): The CPU, chipset, and most peripherals are powered down. Only system RAM remains powered in self-refresh mode to preserve the operating system state.
  • \(S4\) (Hibernate): The contents of RAM are written to non-volatile storage, and the entire system is powered off.

The Fixed ACPI Description Table (FADT) provides the hardware register addresses needed to enter and exit these states. Specifically, it points to the Power Management 1 Control (PM1a_CNT and PM1b_CNT) registers.

To enter a sleep state such as \(S3\), the operating system first executes the _PTS (Prepare to Sleep) AML method, which notifies firmware and embedded controllers of the impending transition. The kernel then saves device states, flushes CPU caches, and writes the sleep type value (SLP_TYP) and sleep enable bit (SLP_EN) to the PM1a_CNT register. The hardware immediately cuts power to the appropriate rails.

When a wake event occurs, such as a power button press or a Wake-on-LAN packet, the hardware restores power to the CPU and jumps to the firmware waking vector specified in the Firmware ACPI Control Structure (FACS). The firmware reinitializes the processor and transfers control back to the operating system kernel, which executes the _WAK (System Wake) AML method and restores device drivers to normal operation.