How Did EEPROM Evolve Into Modern NAND Flash?

Electrically erasable programmable read-only memory laid the foundation for modern non-volatile storage by proving that solid-state memory could be erased and rewritten without physical removal or ultraviolet light. Over several decades, engineers overcame EEPROM's density and cost limitations by reorganizing memory cells into shared-erase blocks, switching from parallel to series cell architectures, and stacking cells vertically in three dimensions to create today's high-capacity NAND flash.

The Foundation: Floating-Gate Transistors and EEPROM

Before EEPROM, non-volatile semiconductor memory relied on EPROM, which required exposing a quartz window on the chip to ultraviolet light to erase data. In the late 1970s, researchers at Intel and Hughes Aircraft developed EEPROM using floating-gate metal-oxide-semiconductor (FGMOS) transistors. By applying a controlled electric field across a thin oxide layer, electrons could be injected onto or removed from an electrically isolated floating gate via Fowler-Nordheim tunneling.

This breakthrough allowed individual bytes to be erased and reprogrammed in-circuit. However, EEPROM required two transistors per bit—one storage transistor and one select transistor—along with complex on-chip routing for byte-level control. As a result, EEPROM was expensive and limited to small capacities, making it suitable for configuration data and firmware rather than mass storage.

The Flash Memory Breakthrough

In the early 1980s, Fujio Masuoka at Toshiba sought a way to dramatically increase memory density while retaining electrical erasability. His solution was flash memory, which eliminated byte-level erasure in favor of erasing entire blocks or sectors simultaneously.

By removing the individual select circuitry needed for single-byte erasure, flash memory reduced the cell size closer to that of a single transistor. This architectural shift traded fine-grained write flexibility for much higher storage density and lower cost per bit, opening the door for solid-state memory to compete with magnetic disks.

From NOR to NAND Architecture

Flash memory initially emerged in two main topologies: NOR and NAND. NOR flash, commercialized by Intel in 1988, connected memory cells in parallel to the bit line. This provided fast random-access reads, making it ideal for executing code directly from memory, but its parallel connections kept cell sizes relatively large.

Toshiba introduced NAND flash in 1989 with a different trade-off. Instead of connecting each cell individually to the bit line, NAND arranged memory cells in series—typically 8, 16, or more cells strung together—resembling a NAND logic gate. Because adjacent cells shared contacts, NAND flash eliminated most of the bit-line contact overhead, shrinking the cell area by roughly half compared to NOR flash. Although NAND could not support fast byte-level random access, its high density and fast sequential page writes made it ideal for mass data storage.

Scaling Beyond Planar Limits: MLC, TLC, and 3D NAND

As demand for portable electronics, smartphones, and data centers grew, manufacturers pushed NAND flash density further through two major innovations:

• Multi-level cell storage: Instead of storing a single bit per cell (SLC), engineers developed precise voltage-sensing circuits to store 2 bits (MLC), 3 bits (TLC), and 4 bits (QLC) per cell by dividing the charge range into \(2^n\) distinct threshold voltage states.
• Charge-trap and 3D vertical stacking: By the early 2010s, shrinking planar floating-gate cells below 15 nanometers caused severe electron leakage and cell-to-cell interference. The industry transitioned to 3D NAND, replacing conductive polysilicon floating gates with insulating silicon nitride charge-trap layers and stacking dozens—and eventually hundreds—of memory layers vertically.

Today, modern 3D NAND flash powers solid-state drives (SSDs), smartphones, and enterprise storage arrays, achieving terabyte-scale capacities on a single die while tracing its core physical principles directly back to the floating-gate innovations of early EEPROM.