Why Cache Line Sizes Are Powers of Two

Modern computer architectures rely on spatial locality to accelerate data access, fetching contiguous blocks of memory whenever a single address is requested. Designing cache line sizes as exact powers of two (such as 32, 64, or 128 bytes) directly matches the binary addressing structure of digital hardware. This mathematical alignment enables instantaneous memory address decoding, eliminates complex arithmetic during memory access, aligns perfectly with standard primitive data structures, and maximizes the hit rate of hardware prefetchers.

Instant Address Decoding via Bit Partitioning

In binary computer architectures, physical memory addresses are fixed-width binary numbers. When cache line sizes are an exact power of two (\(2^k\)), any memory address can be partitioned into three distinct hardware fields without requiring mathematical computation:

• Block Offset (\(k\) bits): Identifies the exact byte within the cache line.
• Index (\(m\) bits): Selects the specific cache set where the line resides.
• Tag (remaining upper bits): Verifies whether the cached line matches the requested physical address.

Because the line size is \(2^k\), extracting the block offset and cache set index requires simple bit-slicing and masking operations (hardware wire routing). If cache line sizes were arbitrary non-power-of-two values, the memory controller would have to perform costly division and modulo operations to calculate line boundaries, introducing severe latency on every memory access.

Efficient Hardware Implementation

Using powers of two avoids dedicated arithmetic logic units (ALUs) inside the memory subsystem. Hardware multiplexers can route addresses directly based on bit positions. Bitwise AND operations and logical shifts replace division:

• To find the start of a cache line: Address AND NOT (Line_Size - 1)
• To find the offset within the line: Address AND (Line_Size - 1)

These operations execute in a fraction of a clock cycle, keeping cache lookup latencies low enough to match high-frequency CPU execution cores.

Natural Alignment with Primitive Data Types

Standard data types (e.g., 2-byte shorts, 4-byte integers, 8-byte pointers and doubles) are inherently sized as powers of two. When cache lines are also sized to powers of two:

1. Elimination of Boundary Crossing: Contiguous arrays of standard data types fit cleanly within line boundaries. An 8-byte double aligned to an 8-byte boundary within a 64-byte cache line will never split across two separate cache lines.
2. Predictable Packing: Arrays and struct layouts pack evenly into the cache block, ensuring that traversing sequential elements leverages spatial locality without triggering unnecessary cache-miss penalties caused by misaligned, multi-line spanning reads.

Optimized Prefetching and Sequential Traversal

Spatial locality assumes that executing code will sequentially read contiguous memory regions, such as scanning an array or executing consecutive instructions. When line sizes are powers of two, hardware stream prefetchers can accurately predict the next target block by simply incrementing the upper address bits (the block address) by one. This allows the memory controller to prefetch entire contiguous blocks into the cache before the CPU explicitly requests them, minimizing stalls and maximizing memory throughput.