Why Adding Two Negative Numbers Causes Binary Overflow

In computer systems, signed integers are typically represented using the two’s complement binary format, where the most significant bit (MSB) indicates the sign of the number. When two negative numbers are added, their sum may exceed the minimum negative value that the fixed bit-width can hold. Because binary adders discard bits that exceed the fixed width, the arithmetic wraps around and inadvertently clears the sign bit to zero, producing an incorrect positive result known as signed overflow.

Two’s Complement and the Sign Bit

To understand signed overflow, it is essential to look at how modern processors store signed integers. In a two’s complement system with a fixed width of \(n\) bits:

• The most significant bit (the leftmost bit) acts as the sign bit: 0 denotes a non-negative number, while 1 denotes a negative number.
• An \(n\)-bit signed integer can only represent values in the range from \(-2^{n-1}\) to \(2^{n-1} - 1\).

For example, in an 8-bit signed integer system: * The minimum representable value is \(-128\) (10000000 in binary). * The maximum representable value is \(+127\) (01111111 in binary).

How Binary Addition Works

Hardware adders perform standard binary addition bit-by-bit from right to left, without inherently differentiating between signed and unsigned values. They add the bits, compute carry values for subsequent positions, and truncate any carry-out that exceeds the fixed bit-width.

Because both operands are negative, both have an MSB of 1. When the adder reaches the MSB position, it must add: \[\text{MSB}_A (1) + \text{MSB}_B (1) + \text{Carry-In}\]

• If the incoming carry from the lower bits is 0: \(1 + 1 + 0 = 10_2\). The resulting sign bit becomes 0, and a carry-out of 1 is generated and discarded.
• If the incoming carry from the lower bits is 1: \(1 + 1 + 1 = 11_2\). The resulting sign bit remains 1, and a carry-out of 1 is generated and discarded.

A Concrete 8-Bit Example

Consider adding \(-70\) and \(-70\) in an 8-bit system:

1. True Mathematical Result:
   \(-70 + (-70) = -140\)
   However, \(-140\) is outside the 8-bit signed range of \([-128, +127]\).

2. Binary Representation:

   • \(-70\) in two’s complement: 10111010
   • \(-70\) in two’s complement: 10111010

3. Performing the Addition:

     Carry:   1 1 1 1 0 1 0 0
              1 0 1 1 1 0 1 0  (-70)
            + 1 0 1 1 1 0 1 0  (-70)
            -----------------
            1 0 1 1 1 0 1 0 0  (9-bit raw result)

4. Truncation to 8 Bits:
   The 9th bit (the carry-out of 1) is discarded by the 8-bit register, leaving: 01110100

5. Interpreting the Result:
   The resulting MSB is 0, which indicates a positive number. Converting 01110100 to decimal gives \(+116\).

Identifying Signed Overflow

Signed overflow happens whenever arithmetic operations push a value outside the representable range of the chosen data type. A processor detects signed overflow during addition using a simple rule:

• If two operands have the same sign (both negative or both positive), and the resulting sum has the opposite sign, a signed overflow has occurred.

In hardware, this condition is formally detected by checking whether the carry entering the sign bit differs from the carry leaving the sign bit (Carry-In to MSB \(\neq\) Carry-Out from MSB). When this occurs, the processor sets the overflow flag (OF) to indicate that the resulting positive value is invalid.