Why 8b/10b Encoding Is Used for DC Balance

In high-speed serial communications, transmitting unencoded binary data can cause severe signal degradation, receiver synchronization failures, and data corruption. 8b/10b encoding resolves these challenges by converting 8-bit data bytes into 10-bit symbols to maintain Direct Current (DC) balance and ensure frequent signal transitions. This article explains how 8b/10b encoding operates, why DC balance is critical for AC-coupled gigabit systems, and how the mechanism facilitates reliable clock recovery.

The Challenge of Raw Serial Data Transmission

In gigabit serial links such as Gigabit Ethernet, PCIe, and SATA, data travels sequentially over a single differential pair rather than across parallel channels. These high-speed physical lines are typically AC-coupled using series capacitors to isolate the DC voltage levels between the transmitter and receiver.

When transmitting raw, unencoded binary data, long sequences of identical bits (all 1s or all 0s) frequently occur. In an AC-coupled link, a long string of identical bits acts like a continuous DC current. This charges the coupling capacitors, shifting the reference voltage level—a phenomenon known as baseline wander. Baseline wander distorts the voltage thresholds at the receiver, making it difficult to distinguish between high and low logic states and resulting in elevated bit error rates (BER).

Maintaining DC Balance with Running Disparity

DC balance requires that the total number of transmitted 1s and 0s remains equal over time, producing an average DC voltage of zero. 8b/10b encoding achieves this by mapping 256 possible 8-bit input values (\(2^8\)) into a subset of 1,024 possible 10-bit output patterns (\(2^{10}\)).

The encoding scheme selects 10-bit symbols that are either perfectly balanced (five 1s and five 0s) or slightly unbalanced (six 1s and four 0s, or four 1s and six 0s). To prevent accumulated charge from unbalanced symbols, the encoder tracks a parameter called Running Disparity (RD), which evaluates to either positive (RD+) or negative (RD-):

  1. Balanced Symbols: If a symbol contains an equal number of 1s and 0s (disparity of 0), the running disparity does not change.
  2. Unbalanced Symbols: Each unbalanced 8-bit byte is assigned two different 10-bit symbols—one with a positive disparity (+2) and one with a negative disparity (-2).
  3. Disparity Compensation: If the current state is RD- and an unbalanced byte is sent, the encoder selects the +2 symbol, switching the state to RD+. The next unbalanced transmission is then forced to use a -2 symbol, resetting the state back to RD-.

This continuous alternating mechanism prevents any long-term accumulation of static charge on the line, eliminating baseline wander.

Ensuring Clock Recovery and Transition Density

Gigabit serial interfaces do not transmit a separate clock line alongside the data stream. Instead, the receiver must extract the timing clock directly from the incoming data using a Phase-Locked Loop (PLL).

For a PLL to stay locked, the incoming data stream must contain frequent voltage transitions (edges from 0-to-1 or 1-to-0). 8b/10b encoding enforces a strict maximum run-length limit of five consecutive identical bits. By guaranteeing frequent transitions, 8b/10b encoding ensures that the receiver’s clock recovery circuit maintains synchronization without drifting, even during idle periods or long repetitive data streams.

Control and Framing Capability

Because the 10-bit space provides significantly more combinations than the original 8-bit space, 8b/10b encoding reserves several unique 10-bit patterns as special control characters (known as K-codes). These codes contain distinct transition sequences, such as “comma” characters, that never appear within normal data streams. Receivers use these unique patterns for word alignment, frame boundaries, and link initialization without corrupting the active data payload.