What Is a SAR ADC and How Does It Work?

A Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) is a widely used data converter that translates continuous analog voltage signals into discrete digital values using a binary search algorithm. This article explains the fundamental architecture of a SAR ADC, details how it utilizes the binary number system to perform efficient conversions bit-by-bit from the most significant bit to the least significant bit, and walks through a step-by-step conversion example.

Core Components of a SAR ADC

A SAR ADC achieves conversion by comparing an unknown input voltage to an internal reference voltage generated step-by-step. The architecture consists of four primary blocks:

  1. Sample-and-Hold Circuit (S/H): Captures and holds the analog input voltage (\(V_{in}\)) constant during the conversion cycle.
  2. Analog Comparator: Compares the held input voltage (\(V_{in}\)) to the internal approximation voltage (\(V_{DAC}\)) generated by the DAC, outputting a high (1) or low (0) digital logic signal based on which voltage is higher.
  3. Successive Approximation Register (SAR Logic): Stores the current digital guess and updates the bits sequentially based on the output of the comparator.
  4. Internal Digital-to-Analog Converter (DAC): Converts the digital code stored in the SAR register back into an analog voltage (\(V_{DAC}\)) to be fed to the comparator.

The Binary Search Mechanism in the Binary Number System

In a positional binary numeral system, each bit represents an explicit power of two:

\[\text{Value} = b_{N-1}2^{N-1} + b_{N-2}2^{N-2} + \dots + b_0 2^0\]

Because each bit position represents a weight equal to the sum of all lower bits plus one LSB (Least Significant Bit), an \(N\)-bit conversion can be resolved in exactly \(N\) sequential clock cycles.

Instead of testing all \(2^N\) possible combinations linearly, the SAR logic performs a classic binary search:

  1. Initialization: All bits in the SAR are reset to 0.
  2. Testing the MSB (Most Significant Bit): The SAR sets the MSB (\(b_{N-1}\)) to 1. This sets the DAC output to the exact midpoint of the full-scale reference voltage (\(V_{ref} / 2\)).
  3. Comparison:
    • If \(V_{in} \ge V_{DAC}\), the input is in the upper half of the range. The MSB remains 1.
    • If \(V_{in} < V_{DAC}\), the input is in the lower half of the range. The MSB is cleared to 0.
  4. Iterating Downward: The SAR moves to the next bit (\(b_{N-2}\)), sets it to 1, and checks the comparator output again. The DAC output becomes either \(V_{ref}/4\), \(3V_{ref}/4\), or the appropriate fractional value depending on the state of previously resolved bits.
  5. Completion: This process repeats for each successive bit until the LSB (\(b_0\)) is determined. Once the LSB is evaluated, the conversion ends, and the final digital word is latched to the output.

Step-by-Step Example (4-Bit ADC)

Consider a 4-bit SAR ADC with a reference voltage \(V_{ref} = 8.0\text{ V}\) and an input voltage \(V_{in} = 5.2\text{ V}\).

The resulting digital output is 1010 (representing \(5.0\text{ V}\), within the quantization error of the converter).

Performance Characteristics