UART Framing: Start, Stop, and Parity Bits Explained

Universal Asynchronous Receiver-Transmitter (UART) serial communication packages binary data into structured units called data frames to transmit information across a single data line without a shared clock signal. Because the transmitter and receiver do not share a common clock line, UART relies on precise timing conventions—defined by the baud rate—and specific framing bits (the start bit, optional parity bit, and stop bits) to synchronize transmission, deliver the binary payload, and detect basic transmission errors.

The Idle State

Before any data transmission begins, the UART transmission line is held at a continuous high voltage level, known in binary logic as a logic 1 or “Mark” state. This sustained high voltage ensures that the receiver can distinguish between an inactive channel and a disconnected or broken line.

The Start Bit

Every UART frame begins with a single Start bit. To initiate transmission, the transmitting device pulls the line from the high idle state (logic 1) down to a low voltage level (logic 0 or “Space”).

This transition from high to low alerts the receiving UART that a data word is arriving. The receiver uses this edge transition to synchronize its internal clock and begins sampling the incoming line at intervals corresponding to the predetermined baud rate, typically sampling at the midpoint of each subsequent bit period.

The Data Word

Immediately following the start bit, the binary data payload is transmitted. The data word typically consists of 5 to 9 bits, with 8 bits (one byte) being the standard configuration.

• Bit Order: Data is almost universally transmitted Least Significant Bit (LSB) first and ends with the Most Significant Bit (MSB).
• Binary Representation: Each bit occupies a precise time slot defined by the baud rate (\(T = \frac{1}{\text{baud}}\)). A high voltage represents a binary 1, and a low voltage represents a binary 0. For example, the ASCII character ‘A’ (binary 01000001) is sent sequentially as 1, 0, 0, 0, 0, 0, 1, 0.

The Parity Bit

Following the data word, an optional parity bit can be added to provide basic single-bit error detection. The parity bit checks the sum of binary 1s in the data payload:

• Even Parity: The transmitter sets the parity bit to 0 or 1 to make the total count of 1s in the data word plus the parity bit an even number.
• Odd Parity: The transmitter sets the parity bit to make the total count of 1s an odd number.
• No Parity (None): The parity bit is omitted entirely, shortening the frame.

When the receiver reads the data bits, it recalculates the parity. If the calculated value does not match the received parity bit, the receiver flags a parity error.

The Stop Bit(s)

The frame concludes with one or two Stop bits (and occasionally 1.5 bit periods). The transmitting UART drives the communication line back to the high voltage level (logic 1).

The stop bit confirms the end of the packet, allows the receiver to verify frame integrity, and resets the line to the idle state. If the receiver does not detect a high logic level during the expected stop bit duration, it registers a “framing error,” indicating a timing mismatch or corrupted data. Once the stop bit duration concludes, the line either remains high (idle) or immediately transitions low to signal the start bit of the next frame.