Johnson Counter Glitch-Free Decoding Explained

This article explores how Johnson counters eliminate transient glitches during state decoding compared to traditional binary counters. By utilizing a modified shift-register architecture that changes only a single bit per clock transition, Johnson counters produce a unit-distance code sequence. This fundamental characteristic removes the race conditions and propagation delay mismatches that typically cause decoding hazards in standard binary systems.

The Cause of Glitches in Binary Decoding

In a standard binary counter, state transitions often require multiple flip-flops to toggle simultaneously. For example, when transitioning from state 3 (binary 011) to state 4 (binary 100), all three bits change state.

Because physical logic gates and flip-flops possess slightly different propagation delays, these bit changes do not occur at the exact same instant. During the transition, the circuit may momentarily pass through intermediate, unintended states such as 010, 001, or 111. When combinational logic gates decode these states, these brief transition intervals produce false output pulses known as glitches or logic hazards.

The Johnson Counter Structure and Sequence

A Johnson counter (also known as a twisted ring or Möbius counter) is constructed using an \(N\)-stage shift register where the inverted output (\(\bar{Q}\)) of the final flip-flop is fed back into the data input (\(D\)) of the first flip-flop.

An \(N\)-bit Johnson counter yields \(2N\) unique states. For a 4-bit Johnson counter (\(Q_0, Q_1, Q_2, Q_3\)), the sequence progresses as follows:

  1. 0000
  2. 1000
  3. 1100
  4. 1110
  5. 1111
  6. 0111
  7. 0011
  8. 0001

Why Johnson Counter Decoding is Glitch-Free

Johnson counter encoding eliminates decoding spikes through two primary mechanisms:

  1. Unit Hamming Distance (Single-Bit Transitions): Between any two adjacent states in the sequence, exactly one flip-flop changes its output logic level. Because only one bit changes at a time, there are no competing transitions between multiple flip-flops, making it physically impossible to generate intermediate transient states.

  2. Simplified Two-Input Decoding Logic: Every state in a Johnson sequence can be uniquely identified by monitoring the state of just two adjacent flip-flops using a simple two-input logic gate (such as an AND, NAND, OR, or NOR gate), regardless of the total length of the counter.

For instance, in a 4-bit Johnson counter: * State 0000 is uniquely identified when \(\bar{Q}_0\) and \(\bar{Q}_3\) are both high. * State 1000 is uniquely identified when \(Q_0\) and \(\bar{Q}_1\) are both high. * State 1111 is uniquely identified when \(Q_0\) and \(Q_3\) are both high.

Because each decoding gate only monitors one bit that is transitioning and one bit that remains stable during any single clock edge, the output transitions cleanly from active to inactive (or vice versa) without overlapping race conditions. This ensures that the decoded outputs remain entirely glitch-free without requiring additional strobing signals or output registers.