How RAS and CAS Decode Binary Memory Addresses

This article explains how Dynamic Random-Access Memory (DRAM) uses Row Address Strobe (RAS) and Column Address Strobe (CAS) signals in conjunction with binary decoding to locate and access individual memory cells. By multiplexing binary address inputs over shared physical pins, memory controllers split addresses into row and column coordinates, activating internal logic gates that isolate specific data bits within a high-density two-dimensional storage grid.

The Two-Dimensional DRAM Grid

DRAM stores individual bits of data inside microscopic cells consisting of a single transistor and a capacitor. To manage billions of these cells efficiently, they are organized in a two-dimensional grid composed of horizontal rows (wordlines) and vertical columns (bitlines). Every unique intersection of a wordline and a bitline represents a single bit location.

Binary Address Multiplexing

A memory address is transmitted by the CPU or memory controller as a binary number. In a system without multiplexing, accessing \(2^N\) memory locations would require \(N\) dedicated physical address lines. To reduce chip size and pin count, modern DRAM uses address multiplexing, splitting the binary address into two separate halves:

  1. Row Address: The upper binary bits designating the horizontal coordinate.
  2. Column Address: The lower binary bits designating the vertical coordinate.

Because both halves travel across the exact same physical address pins at different times, the memory chip relies on the RAS and CAS control signals to determine which part of the binary address is currently present on the bus.

The RAS Phase: Selecting the Row

  1. Address Assertion: The memory controller places the row’s binary value onto the shared address bus.
  2. Signal Activation: The \(\overline{\text{RAS}}\) (Row Address Strobe) signal transitions to an active low state, signaling the memory chip to latch the binary bits present on the pins.
  3. Binary Row Decoding: The binary bits enter an internal row decoder—a network of binary logic gates (such as AND and NAND gates). An \(n\)-bit binary input activates exactly one of \(2^n\) wordlines.
  4. Row Activation: The selected wordline turns on all the access transistors along that row, dumping the stored charge of every cell in that row into a bank of sense amplifiers.

The CAS Phase: Selecting the Column

  1. Address Assertion: With the row contents held in the sense amplifiers, the memory controller places the column’s binary value onto the same address bus pins.
  2. Signal Activation: The \(\overline{\text{CAS}}\) (Column Address Strobe) signal transitions to an active low state, commanding the chip to latch the column address bits.
  3. Binary Column Decoding: An internal column decoder processes the binary column bits, translating the \(m\)-bit input to activate one of \(2^m\) column select lines.
  4. Data Transfer: The active column line opens the corresponding gate in the sense amplifier bank, connecting only the targeted bit (or word) to the input/output (I/O) data buffer for reading or writing.

Summary of the Binary Decoding Process

The complete access cycle relies on translating a flat binary address into sequential coordinates:

\[\text{Full Binary Address} \longrightarrow [\text{Row Bits}] + [\text{Column Bits}]\]

  1. Binary Row Bits \(\xrightarrow{\text{RAS Latch}}\) Row Decoder \(\longrightarrow\) Activates single wordline (Row).
  2. Binary Column Bits \(\xrightarrow{\text{CAS Latch}}\) Column Decoder \(\longrightarrow\) Connects target bitline (Column) to I/O.

Through this coordinated timing of RAS and CAS, DRAM accurately isolates any single memory cell out of millions using a minimal number of physical pins and standard binary logic decoding.